Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).

Abstract: In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.

Abstract: A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a semiconductor device that allows performance to follow a dynamically changing load.

Abstract: A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node.

Abstract: In accordance with embodiments of the present disclosure, a method may include, during boot of a modular information handling system disposed in a chassis configured to receive a plurality of modular information handling systems and a plurality of modular information handling resources, pausing execution of a basic input/output system. The method may also include communicating a first indicator, wherein the first indicator causes a chassis management controller of the chassis to perform link optimization operations of a communication link between the modular information handling system and a modular information handling resource. The method may further include, in response to communication by the chassis management controller of a second indicator, the second indicator indicating completion of link optimization operations by the chassis management controller, unpausing execution of the basic input/output system.

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract: Techniques are provided for actively managing secure boot variables. Such techniques include receiving a request from an entity to modify a portion of a basic input/output system (BIOS), the request including a data segment, and verifying that the requesting entity is authorized to modify a portion of the BIOS. In response to verifying that the requesting entity is authorized, the portion of the BIOS is modified based on the received request and the data segment, and a copy of the data segment is stored in a file on a physical memory that is communicatively coupled to the BIOS. If the BIOS is updated, thereby erasing part or all of the secure boot variables that are stored in the BIOS, the record of changes of the secure boot variables along with default authenticated variables may be used to restore the secure boot variables to a state prior to the BIOS update.

Abstract: According to one embodiment, a setting method, includes storing, in a first partition of a storage which stores a first file causing a processor to execute a first program to booting an operating system, a second file having a same path as a path of the first file and causing the processor to execute a second program. The second program is executed by the processor at activation of an information processing apparatus and causing the processor to execute the first program.

Abstract: In the invention, a first processor that controls operation of a predetermined controlled unit and a second processor are operated in a first mode, a second mode, and a third mode, in the first mode the first processor and second processor are operable respectively, in the second mode respective amounts of power supplied to the first and second processors are lower than that in the first mode, in the third mode respective amounts of power supplied to the first and second processors are an amount between that in the first mode and that in the second mode and at least the predetermined controlled unit is operable, and in the second mode, the first processor puts a process related to the first processor before a process related to the second processor until the second mode is transited to the third mode.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Abstract: Accessory device power management techniques are described in which a power exchange state for a system including a host computing device, an accessory device, and an adapter is recognized. Power exchange states may be defined according to relative states of charge (RSOC) and connection status for the system components and mapped to power management control actions. Responsive to the recognition of a current power exchange state, corresponding power management control actions may be ascertained and applied to jointly manage power for the system. For instance, the host device may draw supplemental power from a power source associated with an accessory device (e.g., a battery or power adapter) or supply power for use by the accessory device according to different states. Power exchanges may also be managed in accordance with capabilities of the accessory device identified based on authentication of the accessory device.

Abstract: An electronic apparatus and a method for resuming from hibernation are disclosed. The electronic apparatus comprises an external storage, a main memory, an image generating circuit and a page moving circuit. The image generating circuit writes pages from the main memory into the external storage to generate a hibernation image file during a hibernation process. The page moving circuit according to the hibernation image file sequentially writes the pages from the external storage back to a continuous page range of the main memory during a resume process. The resume process is later than the hibernation process.

Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).

Abstract: Techniques are disclosed relating to clock routing techniques in processors with both pipelined and non-pipelined circuitry. In some embodiments, an apparatus includes execution units that are non-pipelined and configured to perform instructions without receiving a clock signal. In these embodiments, one or more clock lines routed throughout the apparatus do not extend into the one or more execution units in each pipeline, reducing the length of the clock lines. In some embodiments, the apparatus includes multiple such pipelines arranged in an array, with the execution units located on an outer portion of the array and clocked control circuitry located on an inner portion of the array. In some embodiments, clock lines do not extend into the outer portion of the array. In some embodiments, the array includes one or more rows of execution units. These arrangements may further reduce the length of clock lines.

Abstract: A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line.

Abstract: Methods and apparatus are disclosed for controlling power for a work machine. An example method disclosed herein includes identifying an energy storage level of an energy storage device; identifying a transmission setting of the work machine; and determining whether to control a function of the work machine using power from the energy storage device or power from a second power source different from the energy storage device based on the energy storage level and the transmission setting.

Abstract: A control method and an electronic device are disclosed in the application. The control method is applied to an electronic device including a CPU. The method includes: obtaining a current state of the electronic device; judging whether the current state is a first or a second state; generating a first control instruction in the case that the current state is the first state, or generating a second control instruction in the case that the current state is the second state; performing the first control instruction to control the operating frequency of the CPU within the first maximum operating frequency or performing the second control instruction to control the operating frequency of the CPU within the second maximum operating frequency. Enabling to regulate the maximum operating frequency of the CPU adaptively based on the current state of the electronic device.