Abstract: Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.

Abstract: For each of a plurality of servers, a method includes obtaining current component power consumption values and calculating a current power consumption efficiency. The method further includes determining, for each of the plurality of servers, the current power consumption efficiency and an associated capacity utilization before and during performance of multiple instances of an identified workload. Then, for each server, the method determines a curve of power consumption efficiency as a function of capacity utilization that is representative of the performance of the plurality of instances of the identified workload. Embodiments of the method may then use the curve of power consumption efficiency curve in order to manage the power consumption efficiency of the plurality of servers. For example, the method may assign an additional workload to the server that is identified as having the greatest predicted power consumption efficiency.

Abstract: An image processing apparatus capable of entering a power saving state includes a detection unit configured to detect an object, a determination unit configured to determine whether there is a human hand in a position higher than a predetermined height based on a detection result of the detection unit, and a control unit configured to, if the determination unit determines that there is a human hand in the position higher than the predetermined height, make the image processing apparatus return from the power saving state.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: A non-signal analyzing method for a data storage system including a storage device connected to a host via a data line and a power line includes; communicating a non-signal from the host to the storage device via the power line, detecting the non-signal in the storage device and return the non-signal through to the host via the data line, and analyzing the returned non-signal using a protocol analyzer to generate analysis results characterizing the returned non-signal.

Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).

Abstract: A voltage regulator for delivering power to a processor subsystem within an information handling system is disclosed. The voltage regulator includes an interface to an embedded controller for receiving a linear load line impedance and an intelligent load line controller. The intelligent load line controller may enable linear load line control, determine that a nonlinear load line condition is satisfied, and enable nonlinear load line control based on the determination that the nonlinear load line condition is satisfied.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.