Abstract: The Present disclosure relates to the field of display technology and discloses an array substrate and a curved display device which can solve the technical problem of dark area on both sides of the existing curved display device. The array substrate according to the present disclosure comprises a number of sub pixel units arranged as an array, each sub pixel unit comprising a main sub pixel, a secondary sub pixel and a voltage-dividing capacitor. Said array substrate is divided into a compensation region and a non-compensation region. The capacitance of the voltage-dividing capacitor of the sub pixel unit in the compensation region is smaller than that of the voltage-dividing capacitor of the sub pixel unit in the non-compensation region. The present disclosure is applicable to curved display devices such as curved television and curved display, etc.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.

Abstract: An organic light emitting diode display may include a front display part including a plurality of front pixels formed on a substrate and realizing an image at a front and a side display part. A side pixel of the side display part may include: a plurality of thin film transistors formed on the substrate; a protective layer covering the plurality of thin film transistor and having an inclination groove that is oblique; a first electrode formed at the inclination groove of the protective layer; a pixel defining layer having an opening exposing the first electrode and formed on the protective layer; an organic emission layer formed on the first electrode and the pixel defining layer; and a second electrode covering the organic emission layer.

Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.

Abstract: An organic light emitting display includes a first substrate, a first electrode, a second electrode, a second substrate, and an organic light emitting layer. The first electrode is disposed on the substrate. The second electrode is disposed on the first electrode. The second substrate is disposed on the second electrode. The organic light emitting layer is interposed between the first electrode and the second electrode. The first electrode and the second electrode are reflective. The first electrode and the second electrode are configured to guide light emitted from the organic light emitting layer to the first substrate or the second substrate.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.

Abstract: An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate (20), a first metal layer including patterns of gate electrodes (21, 24) of a first and second TFTs, an active layer (27) and a gate insulation layer (28) are formed on the substrate; forming an etch stop layer film and a photoresist sequentially on the substrate (20), and allowing the photoresist to form a first, second and third regions through gray-scale exposing and developing; forming a pattern of an etch stop layer (29), a connection via hole (30), and a contact via hole (31) respectively in the first, second and third regions through a patterning process; and forming source electrodes and drain electrodes (22, 23,25, 26) of the first and second TFTs. Photoresist of different thicknesses are disposed according to etch depths, thereby avoiding the over-etch of relatively shallow via holes.

Abstract: A covering method including: preparing a mixture containing insulative material and a solvent; applying the mixture over a defective portion; and covering the defective portion with the insulative material by causing the solvent to evaporate from the mixture. In the covering method, the solvent has a boiling point no lower than 178 degrees Celsius, and in the mixture, a weight ratio percentage of the insulative material to the solvent is no lower than 10%. Thus, the defective portion, which may result in a dark spot, can be efficiently covered with insulative material while ensuring that a non-light-emission area that is formed accordingly has the smallest-necessary size and that sufficient insulation is achieved.

Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.

Abstract: An epitaxial silicon wafer includes a bulk wafer having a first doping concentration, a first epitaxial layer formed over the bulk wafer, the first epitaxial layer having a second doping concentration which is higher than the first doping concentration, and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer having a third doping concentration which is lower than the second doping concentration.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

Abstract: The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a n+ source layer to sandwich a field insulating film, a second gate electrode being the same layer as a gate polysilicon and formed at least on the field insulating film, a third gate electrode formed on one of portions of the second source layer to be electrically connected to the second gate electrode, and a second source electrode formed on the other portion of the second source layer.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact.

Abstract: According to one embodiment, a photocoupler includes a light emitting element, a light receiving element, a bonding layer, input terminals, output terminals and a molded resin body. A light emitting element includes a transparent support substrate, a semiconductor stacked body, and first and second electrodes. A light receiving element includes a light reception surface, a first electrode, and a second electrode. A bonding layer is configured to bond the first surface of the support substrate to the light reception surface side of the light receiving element. The bonding layer is transparent and insulative. Input terminals are connected to the first and second electrodes of the light emitting element. Output terminals are connected to the first and second electrodes of the light receiving element. The light reception surface is included in the light emitting surface. An input electrical signal is converted into an output electrical signal.

Abstract: A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

Abstract: A method for manufacturing a semiconductor device includes: forming a photocatalytic layer and an organic compound layer in contact with the photocatalytic layer over a substrate having a light transmitting property; forming an element forming layer over the substrate having the light transmitting property with the photocatalytic layer and the organic compound layer in contact with the photocatalytic layer interposed therebetween; and separating the element forming layer from the substrate having the light transmitting property after the photocatalytic layer is irradiated with light through the substrate having the light transmitting property.