Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active area including a channel region sandwiched between two source/drain regions; an insulation region surrounding the active area from a top view; and a dielectric layer disposed over and in contact with an interface between the insulation region and the source/drain regions. A method of manufacturing the same is also disclosed.

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.

Abstract: A production method for a micromechanical device having inclined optical windows. First and second substrates are provided. A plurality of through-holes is produced in the first and second substrate such that for each through-hole in the first substrate a congruent through-hole is produced in the second substrate, which overlap when the first substrate is placed over the second substrate. A slanted edge region is produced around a respective through-hole in the first and second substrate, the edge region being inclined at a window angle, two slanted edge regions situated on top of each other being congruent in a top view and being inclined at the same window angle. A window foil is provided having a structured window region, which covers the through-hole in a top view of the window foil in each case, the window foil forming an optical window slanted at the window angle above the respective through-hole.

Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Abstract: An organic light-emitting diode display includes an auxiliary connection line on a substrate; an auxiliary cathode on and connected to the auxiliary connection line; a passivation layer covering the auxiliary cathode; an overcoat layer on the passivation layer; a connection terminal connected to the auxiliary cathode on the overcoat layer; an undercut opening on the overcoat layer exposing a portion of the auxiliary cathode, an under area being in the undercut opening and under one side of the connection terminal; a bank having a size larger than the undercut opening and exposing the entire undercut opening; an organic emission layer on a region other than the under area in the undercut opening exposing the portion of the auxiliary cathode; and a cathode directly connected to the exposed portion of the auxiliary cathode on which the organic emission layer is not formed in the under area of the undercut opening.

Abstract: A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 ?m to 1.5 ?m; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 ?m to 1.5 ?m.

Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor layer sequence having an active region configured to emit radiation at least via a main radiation exit surface during operation and a self-supporting conversion element arranged in a beam path of the semiconductor layer sequence, wherein the self-supporting conversion element includes a substrate and subsequently a first layer, wherein the first layer includes at least one conversion material embedded in a matrix material, wherein the matrix material includes at least one condensed sol-gel material, wherein the condensed sol-gel material has a proportion between 10 and 70 vol % in the first layer, and wherein the substrate is free of the sol-gel material and the conversion material and mechanically stabilizes the first layer.

Abstract: A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus that make it possible to estimate a normal vector to one direction with high accuracy with a simple configuration. A polarization image sensor includes a plurality of polarizers disposed on a chip and having different polarization directions, and a plurality of photoelectric conversion sections having light reception regions for receiving light transmitted through the polarizers, the light reception regions being symmetrical. The present disclosure can be applied, for example, to a polarization image sensor or the like that estimates a surface and a shape of an imaging object.

Abstract: A semiconductor device includes a semiconductor substrate comprising an upper surface and a lower surface, an upper electrode provided on the upper surface, and a lower electrode provided on the lower surface. The semiconductor substrate includes, in a planar view, a first section including a center of the semiconductor substrate and a second section located between the first section and a peripheral edge of the semiconductor substrate. The first and second sections each comprise a MOSFET structure including a body diode. The MOSFET structure in the first section and the MOSFET structure in the second section are different from each other such that a forward voltage drop of the body diode in the first section with respect to a current density is higher than a forward voltage drop of the body diode in the second section with respect to the current density.

Abstract: An image sensor package including an image sensor chip including an active pixel sensor region and a non-sensing region, a plurality of chip pads being in the non-sensing region; a printed circuit board on one side of the image sensor chip, the printed circuit board including a plurality of bonding pads; conductive wires respectively connecting the plurality of chip pads to the plurality of bonding pads; a bonding dam at a periphery of the active pixel sensor region; a cover glass on the bonding dam and facing another side of the image sensor chip; and an encapsulation layer covering a side surface of the bonding dam, a side surface of the cover glass, an edge of a lower surface of the cover glass, the non-sensing region, and an edge of an upper surface of the printed circuit board, wherein the bonding dam is spaced apart from an end of a side surface of the image sensor chip by a distance of 80 ?m to 150 ?m has a height of 50 ?m to 150 ?m from the image sensor chip, and has a width of 160 ?m to 240 ?m.

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

Abstract: A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.

Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).

Abstract: A semiconductor package includes a first semiconductor die, a first substrate, a second semiconductor die, and a second substrate. The first substrate is disposed on the first semiconductor die and includes a plurality of first metal line layers vertically spaced apart from each other, and each of the first metal line layers is electrically connected to one of the followings: a ground source and a plurality of power sources of different types. The second semiconductor die is disposed on the first substrate. The second substrate is disposed on the second semiconductor die and includes a plurality of second metal line layers vertically spaced apart from each other, and each of the second metal line layers is electrically connected to one of the followings: the ground source and the power sources of different types.

Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.

Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

Abstract: Disclosed are a curved display apparatus and a method of manufacturing the same, which improve a luminance difference between a flat part and a curved part. The curved display apparatus having a flat part and a bending part extending from one side of the flat part, either of the flat part and the bending part defining a plurality of emission areas therein, wherein the curved display apparatus comprises: a light emitting device layer including a plurality of light emitting devices to form the emission areas, wherein a slope film is provided in the bending part such that an emission surface of the emission areas in the bending part is almost parallel to an emission surface of the emission areas in the flat part.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.