Abstract: In one aspect, a movable barrier operator system is provided that includes a motor configured to be coupled to a movable barrier. The motor has a power rating indicative of a minimum power to be supplied to the motor in order for the motor to move the movable barrier. The system further includes an external power supply configured to connect to an electrical outlet. The external power supply has a plurality of outputs each having a power rating indicative of a maximum power the output supplies, the output power rating being less than the motor power rating. The movable barrier operator system includes combiner circuitry configured to combine power from the outputs of the external power supply and provide the combined power to the motor. The system further includes a monitoring circuit configured to detect a fault condition of any of the outputs of the external power supply.

Abstract: Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.

Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The pre-conditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.

Abstract: Disclosed embodiments include a system and method of acquiring operating parameter data of a motor system that includes an electric motor. The motor system may be provided as a component of a fan. An embodiment includes recording states of operating parameters during operation of the motor system, wherein the operating parameters include a basic parameter and at least one additional parameter; determining a state-change event of the basic parameter based on a recorded state of the basic parameter; recording a state of the additional parameter upon detection of the state-change event of the basic parameter; linking the recorded state of the additional parameter to the detected state-change event; and storing the recorded state of the additional parameter linked to the detected state-change event.

Abstract: An electronic device is provided. The electronic device includes a first substrate having a peripheral area, a first inorganic layer disposed on the first substrate, an insulating layer disposed on the first inorganic layer and formed a recess, and a second inorganic layer disposed on the insulating layer and formed in the recess. The recess is disposed in the peripheral area. A thickness of the second inorganic layer is less than a thickness of the insulating layer.

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract: An electronic component mounting structure is an electronic component mounting structure in which an electronic component group is mounted on a substrate, and a pattern constituting a part of a current path between the inflow port and the outflow port, the electronic component group includes a plurality of electronic components connected between the inflow port and the outflow port, each of the electronic components has a current inflow terminal electrically connected to the inflow port and a current outflow terminal electrically connected to the outflow port, and one of a first spatial distance group and a second spatial distance group has equal spatial distances within the one spatial distance group, and the first spatial distance group includes spatial distances between the inflow port and the inflow terminals, and the second spatial distance group includes spatial distances between the outflow port and the outflow terminals.

Abstract: A wafer placement table includes: an electrostatic chuck that is a ceramic sintered body in which an electrode for electrostatic adsorption is embedded; a cooling member which is bonded to a surface on an opposite side of a wafer placement surface of the electrostatic chuck, and cools the electrostatic chuck; a hole for power supply terminal, the hole penetrating the cooling member in a thickness direction; and a power supply terminal which is bonded to the electrode for electrostatic adsorption from the surface on the opposite side of the wafer placement surface of the electrostatic chuck, and is inserted in the hole for power supply terminal. The outer peripheral surface of a portion of the power supply terminal is covered with an insulating thin film that is formed by coating of an insulating material, the portion being inserted in the hole for power supply terminal.

Abstract: A power tool may include an end effector configured to enable a fastener to be applied by the power tool via a fastening cycle, a power unit, a drive assembly configured to apply drive power to the end effector responsive to application of input power thereto, and a motor configured to supply the input power to the drive assembly selectively based on operation of a power control assembly that controls coupling of the motor to the power unit. The drive assembly includes a clutch configured to interrupt application of the drive power at a target torque. The power control assembly may be configured to adaptively change speed of the motor in response to the power tool reaching a predefined torque value that is less than the target torque during the fastening cycle.

Abstract: A tandem photovoltaic device includes: a tunnel junction between an upper cell unit and a lower cell unit. The lower cell unit is a crystalline silicon cell. The tunnel junction includes: a carrier transport layer, a crystalline silicon layer, and an intermediate layer located between the carrier transport layer and the crystalline silicon layer. The carrier transport layer is a metal oxide layer. The intermediate layer includes a tunneling layer. The crystalline silicon layer has a doping concentration greater than or equal to 1017 cm?3. The carrier transport layer is in direct contact with a shadow surface of the upper cell unit. If the crystalline silicon layer is a p-type crystalline silicon layer, a first energy level is close to a second energy level. If the crystalline silicon layer is an n-type crystalline silicon layer, a third energy level is close to a fourth energy level.

Abstract: An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy. A method of assembling the apparatus by contacting the substrates.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Abstract: A power module includes a power circuit and a magnetic assembly. The power circuit includes at least one switch element. The magnetic assembly includes at least one first electrical conductor and a magnetic core module comprising at least one hole, wherein the at least one first electrical conductor passes through the at least one hole, and a terminal of the at least one first electrical conductor is electrically connected to the at least one switch element. The power circuit and the magnetic assembly are arranged in sequence along a same direction.

Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.

Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

Abstract: Module for operational control of the guided advance/withdrawal device of the needle added to the smart substance injection device on board equipment for inoculating substances inside a fertile egg and smart method for injection inside a fertile egg, wherein the “inoculation of substances” inside a fertile egg, be this into the embryo, in the case of vaccines, and even into the amniotic fluid, in the case of a nutrient or nutritional vaccine complex, allows the injection needle (11) to be brought close at a controlled speed.

Abstract: A circuit card assembly is described. The circuit card assembly adapts a host circuit card assembly of a host device with an expansion card. By such adaption, the host device may communicate with an access point of an avionics network. The circuit card assembly includes an interface for receiving power from the host circuit card assembly. The circuit card assembly then continuously and selectively provides power to a second interface based on the availability of aircraft power. The second interface receives the expansion card. The circuit card assembly also includes one or more coaxial RF connectors for receiving modulated signals from the expansion card. The circuit card assembly also includes an antenna which transmits radio waves based on the modulated signals. A system for communication to an access point of an avionics network includes the circuit card assembly.

Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.