Abstract: A data receiving method used in a powerline environment is used for converting a modulated signal received from a powerline over a data period within a predetermined clear zone after one zero crossing point of the powerline into a data bit. Each data period includes at least one predetermined bit period. The modulated signal is received within the bit period of one data period. The method includes: detecting zero crossing points of the powerline and generating a SYNC signal when a zero crossing point is detected; converting signals contained within the bit period of a data period after each SYNC signal into digital samples; generating an adaptive threshold according to the digital samples converted from the bit periods of a plurality of data periods; and converting the digital samples converted from the modulated signal into the data bit by using the adaptive threshold.

Abstract: A data transmission method entails differentially transmitting low-pass filtered first outgoing data to and through an isolation transformer at a first data rate. Second outgoing data is differentially transmitted to and through the transformer in the same direction as the first outgoing data but at a second data rate different from, typically greater than, the first data rate. The so-transmitted first and second outgoing data is coupled from the transformer to a communication cable during different time intervals. A related data reception method involves coupling incoming data from a communication cable to and through the isolation transformer and providing the so-coupled incoming data differentially along data transfer paths that extend from the transformer to and through where data moving at the first data rate is received to where data moving at the second data rate is received such that the data transfer paths have a largely constant characteristic impedance.

Abstract: A data-transmitting apparatus contains first and second transmitters, a transmit transformer, and a connecting unit for coupling the transformer to an outgoing twisted-pair cable. The first transmitter filters data to produce outgoing data transmitted to the transformer at a first data rate. The second transmitter transmits outgoing data to the transformer at a different, typically greater, second data rate. A data-receiving apparatus contains first and second receivers, a receive transformer, and a connecting unit for coupling an incoming twisted-pair cable to the receive transformer. The first and second receivers receive incoming data from the secondary winding respectively at the first and second data rates. Incoming data is typically provided along data transfer paths that extend from the receive transformer in a daisy chain manner to the receivers. Data moving at either data rate can be transmitted and received without the need for hot switching in the data paths.

Abstract: A slope detector and method of detecting a slope of the passband signal spectrum in a quadrature amplitude modulation (QAM) digital radio system. The detector operates in baseband for comparing signal output powers of upper and lower sidebands of a received passband signal. The slope detector includes transversal filters for filtering I and Q channel inputs and multipliers and combiners for processing the filter outputs to provide an output that is indicative of the slope of the passband signal spectrum. The output may be a value that is translated to an instantaneous slope, or may be tri-state and indicate whether the slope is positive, zero, or negative.

Abstract: A synchronous clock controller for a digital exchange accommodates installation of a plurality of office line cards. A priority encoder encodes priority information signals respectively provided from the office line cards, and generates a selection signal indicating one of the office line cards having a highest priority among the office line cards in dependence upon the priority information signals. A clock selector receives office line clock signals respectively provided from the office line cards, and outputs a selected one of the office line clock signals provided from the office line card indicated by the selection signal. A digital phase synchronizing circuit phase synchronizes the selected office line clock signal with an internal reference clock signal, and generates a reference synchronization clock signal and a bit synchronization clock signal in response to the phase synchronizing.

Abstract: A transferred data recovery apparatus capable of recovering transferred data from a transferred data signal has a first comparator for comparing transferred data signal with a reference level R to output binary-quantized data signal representing whether or not the transferred data signal is higher than the reference level R. A sample and hold circuit is driven by a clock signal and samples the binary quantized data signal each clock period to output sampled digital data to an averaging circuit. The averaging circuit sequentially averages a predetermined number of the sampled digital data each clock period to produced averaged outputs. A second comparing circuit digitally compares the averaged outputs against an upper reference level and a lower reference level dependent upon the direction of change to produce a recovered data output. The recovered data output goes low when the averaged output goes lower than the lower reference level and goes high when the averaged output goes above the upper reference level.

Abstract: An apparatus and method for recovering packet data with unknown delays and error transients is disclosed that includes a received waveform containing a desired information signal relative to a fixed reference, for eliminating an undesired error in the received waveform where the error is localized in time relative to the received waveform to a transient interval, and recovering the desired information signal. Included also is a sampler, responsive to the received waveform, providing a series of time samples representative of the received waveform. A buffer, responsive to the time samples, for providing a plurality of representations of the received waveform at different instants of time, where the length of time is an appreciable duration of a transient interval. A reference slicker, responsive to the plurality of representations, for providing an estimate of a fixed reference.

Abstract: A modulated clock MSK modulator that separately modulates a sinusoidal clock signal by square wave I and Q digital data signals prior to the I and Q data signals being modulated onto a carrier wave signal. Mixers or applicable biphase switches are utilized to impress the I and Q digital data signal information onto the clock signal by inverting or non-inverting the clock signal on separate I and Q data rails to create I and Q modulated clock signals separated in phase. The I channel data modulated clock signal and the Q channel data modulated clock signal are then separately applied to a conventional quadraphase modulator to be separately modulated onto a carrier wave signal, and the summed together to be transmitted.

Abstract: In a digital audio broadcasting (DAB) system having a radio-frequency (RF) transmitter and a corresponding RF receiver, a system and method for providing improved frame synchronization is provided. In accordance with the preferred embodiment, the RF transmitter formats a DAB signal into a sequence of frames, each frame having a header with a predefined grouping of psuedo-random number sequences comprising 100 symbols. Of these 100 symbols, 86 symbols of the header preferable are used for frame synchronization and characterization of a communications channel, while the remaining 14 symbols are used for interleaver and data synchronization in an interleaved fashion. The formatted DAB signal, including the frame sequences, is transmitted to the receiver preferably using quadrature phase-shift keying modulation. At the receiver, a correlator, utilizing a synchronization detection algorithm, is generally designed to match a predetermined symbol pattern within the received signal.

Abstract: A method for transmitting information by radio over a wide bandwidth comprises the steps of: inputting a data signal into a time varying filter modulator; spreading the data signal in time and in frequency to produce a wideband signal; modulating the wideband signal onto an RF carrier to provide an RF output signal; and transmitting the RF output signal. The step of spreading includes performing a series of linear transformations to the data signal.

Abstract: Real time switch overs from one set of timing signals to a redundant set of timing signals in an ATM system, as required by periodic maintenance checks, are accomplished without incurring data errors by this apparatus and method. Each switch over apparatus has a phase locked loop with a controlled control loop which assists the phase locked loop in rapidly achieving nearly perfect phase locks to one of multiple system reference clocks. The characteristics of the special phased locked loop provide the stability and the timing functions necessary for switch overs between reference clocks to produce errorless ATM signal handling.

Abstract: The present invention provides a double delay-locked loop(DDLL) code tracking loop for spreading a linear section of an energy detecting area of the tracking loop by using several code time, and provides a delay-locked loop code tracking system for a receiver of a code spread communication system capable of performing an effective code tracking even when a changing ratio of a receiving path is large, by variably using a difference of a preceding time code and a delayed time code according to a change of a receiving environment being changed without cease. Accordingly, the code tracking loop of the present invention improves the receiver performance of the code spread radio communication system, and simplifies a structure of the receiver.

Abstract: In a method of detecting reference symbols in a digital data stream constituted by successive frames, each frame contains R reference symbols and I information symbols, and the R reference symbols are uniformly spaced apart in the digital data stream. The received signal is sampled with a period T.sub.e =T.sub.s /N.sub.e, where N.sub.e is an integer not less than 2, and T.sub.s is the symbol time. A cross-correlation is calculated, with each calculated cross-correlation supplying a magnitude I.sub.n equal to: ##EQU1## where x.sub.n+dNe represents the sample received at instant n+dN.sub.e, S*.sub.d,k represents the complex conjugate of the reference symbol of index d, k .epsilon. {0, . . . , R-1} and represents frame index, r=R/q, where q is an integer not less than 1. The cross-correlations are summed over M frames so as to form energy levels J.sub.M,d equal to: ##EQU2## where m is the frame index, M is the number of sums performed, and d .epsilon. {0, . . . , N.sub.e (R+1)-1}.

Abstract: An automatic frequency control circuit comprises an quadrature demodulation unit for creating an in-phase signal and an antiphase signal by quadrature-demodulating a Gaussian Minimum Shiftkeying signal and supplying an electric field strength signal exhibiting an electric field strength of the Gaussian Minimum Shiftkeying signal as well as the created in-phase and antiphase signals; a quality judging unit for judging the quality of the Gaussian Minimum Shiftkeying signal and creating an automatic frequency-controlling data indicating a compensation amount in accordance with the obtained quality signal; a converter for converting into digital signals the in-phase signal, antiphase signal and electric field strength signal supplied from the quadrature demodulation unit and converting the automatic frequency-controlling data into an analog signal; a temperature compensated crystal oscillation circuit for compensating the frequency of the GMSK signal on the basis of the compensation amount indicated by the automa

Abstract: An apparatus for use in a receiver (100) of a wireless communication system is provided. The apparatus comprises a first filter (340) having a first cutoff frequency, a second filter (350) having a second cutoff frequency, a first data bit estimator (360) coupled to the first filter (340), a second data bit estimator (361) coupled to the second filter (350), a third data bit estimator (363), and decision logic (370) dynamically selecting one of the first and second filters based on a first bit count from the first data bit estimator (360), a second bit count from the second data bit estimator (361), and a third bit count from the third data bit estimator (363).

Abstract: A digital radio communications receiver for determining a frame structure even in the event of miss or false detection of a frame structure flag.

Abstract: A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase lock loop controller. Matching pairs of transmission lines interconnect successive stages of the set. One transmission line of each pair connects the output of the first delay circuit of each stage to the input of the first delay circuit of a next stage of the set. The other transmission line of the pair connects the input of the second delay circuit of the stage to the input of the first delay circuit of the next stage. When the first delay circuit of the first stage of the set receives an input reference clock signal, that reference clock signal propagates through all the first delay circuits of each stage in succession. Whenever the input reference clock signal reaches a stage, it also travels back to the second delay circuit of the preceding stage.

Abstract: An initial phase-loading circuit (IPLC) for a fractionally-spaced linear equalizer (FSLE) includes a signal coupling component adapted to be coupled to the FSLE in a configuration so as to selectively introduce time-shifted discrete signals. The FSLE includes a set of initial filter tap coefficients that provide a discrete signal to the FSLE, perform discrete signal equalization using the FSLE at least until substantial convergence of the filter tap coefficients, and provide to the FSLE a time-shifted discrete signal to replace the previously provided discrete signal.

Abstract: A decoding apparatus (200) decodes a coherent, differentially encoded multi-level phase shift keying (DEPSK) modulated signal. A coherent receiver (101) receives and, subsequently, outputs the coherent DEPSK modulated signal to a metric computer (201). The metric computer (201) generates a soft decision metric .LAMBDA.(s(n)) corresponding to the coherent DEPSK modulated signal which is outputted to a forward error correction (FEC) decoder (107). The FEC decoder (107) decodes the coherent DEPSK modulated signal in accordance with the soft derision metric .LAMBDA.(s(n)) corresponding to the coherent DEPSK modulated signal.

Abstract: In a receiver for receiving a carrier modulated with data, there is provided a system for locating and tracking said carrier. The carrier is located by sweeping a frequency range containing said carrier. False lockup are inherent when a wide frequency sweep demodulator attempts to lock onto a carrier, and the system recognizes such lockups by monitoring data from a Viterbi error correction circuit. On false lockup, the system breaks the lockup and continues the sweep until the true data carrier is located and tracked.