Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.

Abstract: A method of operating an inductively coupled plasma mass spectrometry apparatus for analyzing an analyte sample, the mass spectrometry apparatus including a plasma ion source, a mass analyzer and an interface arrangement positioned between the plasma ion source and the mass analyzer of the mass spectrometer, the interface arrangement at least including an interface structure, including a sampling or skimmer cone, and at least one passage with an inlet and an outlet into a reaction zone, the method including: generating a plasma using the plasma ion source and forming a plasma flux to flow towards the mass analyzer; supplying the analyte sample into the reaction zone via the passage such that the analyte sample interacts with the plasma flux; and analyzing the analyte sample using the mass analyzer.

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

Abstract: A transformer for use in a rail vehicle and/or for rail applications, including a core which is at least partially surrounded by at least one coil is, with regard to the objective of providing a transformer in which the geometry of a coil can be selected to be as variable as possible, characterized in that the core is produced from individual segments, wherein the total cross-sectional surface-area of the core is greater than or equal to the sum of the individual cross-sectional surface-areas of the segments and wherein at least two individual cross-sectional surface-areas differ from each other and/or from the total cross-sectional surface-area in terms of their size and/or geometric shape.

Abstract: A policy improvement method of improving a policy of reinforcement learning based on a state value function is performed by a computer. The method causes a computer to execute a process including: calculating an input to a control target based on the policy and a predetermined exploration method of exploring for an input to the control target in the reinforcement learning; and updating a parameter of the policy based on a result of applying the calculated input to the control target, using the input to the control target and a generalized inverse matrix regarding a state of the control target.

Abstract: A method for measuring the concentration of fluorine gas (F2) contained in a halogen fluoride-containing gas using an analysis apparatus having a halogen fluoride-containing gas supply source, a fluorine-containing gas supply source, a tube, a capillary, and a mass spectrometer, the method including, before measuring the concentration of fluorine gas, performing passivation treatment on the tube and the capillary using a passivation gas containing a fluorine-containing gas supplied from the fluorine-containing gas supply source.

Abstract: A method for switching a base station, a mower and a multi-base station working system are provided. The method includes: obtaining, when the number of first common-view satellites between the mower and a first base station is less than a first threshold, the number of second common-view satellites between the mower and a second base station; when the number of the first common-view satellites is less than a second threshold and the number of the second common-view satellites is greater than the second threshold, obtaining the first trajectory of the mower based on the first base station and the second trajectory of the mower based on the second base station; determining, based on the first and second trajectories, a coordinate transformation matrix; and switching from the first base station to the second base station based on the coordinate transformation matrix, the second threshold being less than the first threshold.

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

Abstract: A method and a device can be used to transmit data onboard a watercraft using an onboard power supply network. A central control unit generates an instruction for a first consumer module. The instruction is transmitted from the central control unit via a first control unit-head station data connection to a first head station. The first head station converts the instruction into an instruction signal that is transmittable via the power supply network. The instruction signal is transmitted from the first head station via a first head station-power line data connection, the power supply network, and a first coupling module-power line data connection to a first coupling module. From the instruction signal, the first coupling module again generates an instruction that can be transmitted via a data connection. The instruction is transmitted from the first coupling module via a first coupling module-consumer data connection to the first consumer module.

Abstract: A method for the etching of deep, high-aspect ratio features into silicon carbide (SiC), gallium nitride (GaN) and similar materials using an Inductively-Coupled Plasma (ICP) etch process technology is described. This technology can also be used to etch features in silicon carbide and gallium nitride having near vertical sidewalls. The disclosed method has application in the fabrication of electronics, microelectronics, power electronics, Monolithic Microwave Integrated Circuits (MMICs), high-voltage electronics, high-temperature electronics, high-power electronics, Light-Emitting Diodes (LEDs), Micro-Electro-Mechanical Systems (MEMS), micro-mechanical devices, microelectronic devices and systems, nanotechnology devices and systems, Nano-Electro-Mechanical Systems (NEMS), photonic devices, and any devices and/or structures made from silicon carbide and/or gallium nitride.

Abstract: Kart tracks are provided that can include a magnetic support material below a polymeric coating. Karts are provided that can include processing circuitry operatively coupled to at least one motion sensor and at least one kart control assembly. Methods for controlling passenger operated amusement karts are also provided. Karts are also provided that can include at least one lateral interchangeable battery assembly. Methods for providing power to a passenger operated amusement kart are also provided. Karts are also provided that can include an articulating chassis. Methods for traversing passenger operated amusement kart tracks are also provided. Kart wheel assemblies are also provided. Methods for engaging a passenger operated amusement kart to a track are provided.

Abstract: A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.

Abstract: A network device may receive a request for authentication data, for a UE attempting to register with a network, and an indication that a SUCI utilized by the UE is unencrypted, and may request, from a data store, the authentication data for the UE. The network device may provide, to the data store, a notification instructing the data store to push a UE parameters update (UPU) once a registration process is complete for the UE, and may receive the authentication data from the data store. The network device may complete the registration process for the UE based on the authentication data, and may receive the UPU from the data store based on the registration process being completed. The network device may cause the UE to detach from the network after utilizing the UPU, and may cause the UE to reconnect to the network with an encrypted SUCI.

Abstract: A touch sensor may include a substrate and may include electrode units, first demultiplexers, second demultiplexers, and driving pads all located on the substrate. The electrode units each may include a plurality of electrode groups, the electrode groups each including a plurality of touch electrodes. The first demultiplexers each may include a plurality of sub-demultiplexers and each may be electrically connected to a corresponding one of the electrode units. Each of the sub-demultiplexers of a first demultiplexer may be electrically connected to a corresponding one of the electrode groups of a corresponding electrode unit. The second demultiplexers may be connected between the first demultiplexers and the driving pads.

Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.

Abstract: Disclosed are a rod-shaped sodium ion positive electrode material, a preparation method therefor and an application thereof. The material comprises a rod-shaped base material and nanofibers inserted into the base material. C—Na is loaded on the nanofibers. The chemical general formula of the rod-shaped sodium ion positive electrode material is Na(FeaTb)PO4/CNF-c(C—Na), and 0.001?c?0.1, wherein T is at least one of Ni, Co, Zn, Mn, Fe, V, Ti or Mo, 0.9?a<1, 0<b?0.2, and 0.001?c?0.1. In the present invention, on one hand, some transition metal elements are doped to improve the electrochemical performance thereof, and on the other hand, a modulator is added to synthesize the rod-shaped sodium ion positive electrode material, and the C—Na loaded nanofibers are added to adjust the proportion of large and small rod-shaped materials, so that the composition of a single Na(FeaTb)PO4 rod-shaped nanostructure is optimized.

Abstract: A power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power source, and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boosted voltage according to the reference voltage and a clock signal, and generate a read voltage based on the second boosted voltage according to the control signal. The read voltage is provided to a memory cell array to perform a data reading operation.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.