Abstract: A new DRAM architecture, HPPC DRAM, is provided to support a high performance and low cost memory system. The HPPC DRAM has integrated the following concepts into a single DRAM chip. First, superset pin definitions backward-compatible to the traditional fast-page-mode DRAM SIMM. This allows one memory controller to support a memory system having both a traditional fast-page-mode DRAM and HPPC DRAM of this invention. Secondly, combining a memory array, a register of 4:1 Mux/Demux function, a RAS buffer/decoder, a CAS buffer/decoder, a burst address counter, a page register/comparator, a sequencer and a data buffer into a single DRAM IC chip. Using these intelligent peripheral circuits, the HPPC DRAM execute a pipeline cycle request and precharge cycle stealing. Thirdly, a precharge cycle stealing pipeline is implemented to the timing chain of read operation to eliminate the precharge cycle time which is achieved by executing read drive concurrently to the precharge cycle.

Abstract: In a memory management method for a computer with a hard disk drive, the hard disk drive is first partitioned into at least one system disk drive for storing system files therein, a data disk drive, a system buffer space and a read/write table. Thereafter, the computer is selectively operated in one of an unrestricted mode, where storing of the system files and modifying of the system files in the system disk drive by the computer are permitted, and a restricted mode, where modified portions of the system files in the system disk drive are stored by the computer in the system buffer space instead of the system disk drive to maintain the system files in the system disk drive in their initial form and where the read/write table is updated by the computer to record addresses of the modified portions in the system buffer space and addresses of portions of the system files in the system disk drive corresponding to the modified portions therein.

Abstract: A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the first level cache. In addition, an instruction/data bit in the inclusion vector indicates whether a portion of that line is in the instruction cache at all. Thus, when a snoop is done to the level two cache, additional snoops to the level one cache only need to be done for those lines which are indicated as present by the inclusion vector.

Abstract: The address used to specify the storage location of data streaming from a first device to a second device is used in the control of a data function, such as an XOR function circuit in an integrated PCI buffer controller and data function circuit. An alias PCI address is loaded in a SCSI command block for the data destination when the data function circuitry is to be enabled. A host adapter system driver or application is notified of an alias address during initialization, and uses the alias address in the construction of SCSI command blocks to specify that the data shall be operated upon by the data function. When no data operation is desired, the normal (non-alias) address is specified in the SCSI command block. Thus, for every address for the device, there is a corresponding alias address which not only addresses the same location, but also turns on the data function. In effect, two devices are defined in the address space corresponding to the two modes of operation.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: An address generator has a designating value storing section for storing a designating value for designating each of register sections of an offset register into an address register. The address generator also has a designating value storing section for storing a designating value for designating each of register sections of a modulo register into the address register. Each of the register sections of the offset register and each of the register sections of the modulo register are automatically designated by designating the address generator. In this address generator, a degree of freedom of addressing can be increased while an increase in hardware scale is avoided as much as possible.

Abstract: A computer processor (110) automatically generates block-size operand references during execution of standard instructions. As such a standard instruction is executed, the processor (110) continually examines the number of bytes to be moved (342) and the relative alignment of the operand address (352). At any time during instruction execution, if the operand address is zero modulo the block size, and at least a block sized number of bytes remain to be moved (354), the operand transfer is marked as a block-sized reference.This provides a convenient method for generating block-sized memory references to/from the targeted address space, independent of cache modes such as copyback, write-through, or non-cacheable. This may produce burst accesses, maximizing performance of the data transfer. Additionally, cache memory writes can be optimized to avoid cache line fill reads.

Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

Abstract: An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the denominator is fixed for the calculations, such as address calculations in massively parallel, distributed memory processor systems. Also described is a method and apparatus using the integer-division-by-an-constant method and apparatus, which facilitates removing power-of two restrictions on the reorganization and redistribution of data between remote and local memory blocks in a massively parallel, distributed-memory processing system. The flexible addressing scheme provided supports data organizations which vary widely depending on the processing task. In particular, a plurality of processing elements (PEs) operating in parallel within a subset of all the PEs in a massively parallel processor system, may simultaneously operate on an array data structure, the array data structure having an arbitrary size and shape.

Abstract: A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.

Abstract: When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

Abstract: In a multi-processor system, a page descriptor can be updated in a memory coupled to a processor without stopping operations of other processors. Each processor has a page descriptor comparator including a calculated address register which stores a physical page address for an address calculation, and an updated address register which stores a physical page address to be updated. The page descriptor comparator also has a reset page descriptor (RSTPD) mode register which indicates a mode of the processor, and a coincidence detector. If the RSTPD mode register is active, the coincidence detector detects coincidence between the calculated address register and the updated address register.

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract: To provide fast access times with very large key fields, an associative memory utilizes a location addressable memory and lookup table to generate from a key the address in memory storing an associated record. The lookup tables, stored in memory, are constructed with the aid of arithmetic data compression methods to create a near perfect hashing of the keys. For encoding into the lookup table, keys are divided into a string of symbols. Each valid and invalid symbol is assigned an index value, such that the sum of valid index values for symbols of a particular key is a unique value that is used as an address to the memory storing the record associated with that key, and the sum of keys containing invalid index values point to a location in memory containing similar data. Utilizing the lookup tables set and relational operations maybe carried out that provide a user with a maximum number of key records resulting from a sequence of intersection, union and mask operations.

Abstract: A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device.

Abstract: A method of locating a memory address of a nonvolatile memory card that corresponds to an external address in an integrated circuit card controller that controls memory operation of the card is described. The controller includes a first memory address mapping window and a second memory address mapping window, each storing one of a first and a second set of memory addresses of the nonvolatile memory card. The method includes the steps of accessing the first window for the memory address associated with the external address when external circuitry accesses the nonvolatile memory card with the external address. If the first window has the memory address, then the first window is accessed for the memory address. If the first window does not have the memory address, then the second window is accessed for the memory address. If the second window does not have the memory address, then the second window is updated with a third set of memory addresses of the nonvolatile memory card.

Abstract: To provide for fast access times with very large key fields, an associative memory utilizes a location addressable memory and look up tables to generate from a key an address in memory storing an associated record. The look up tables, stored in a memory, are constructed with the aid of arithmetic data compression methods to create a near perfect hashing of the keys. For encoding into the look up table, keys are divided into a string of symbols. Each symbol is assigned an index value, such that a modulo sum of index values for symbols of a particular key is a unique value that is used as an address to the memory storing the record associated with that key.

Abstract: An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data.