Abstract: In one embodiment, a system includes a disk cache and a controller configured to create a cache resident partition in the disk cache, the cache resident partition being configured to store data thereto that is not subject to HSM, manage the cache resident partition to have a size that is greater than a first minimum size and less than or equal to a total size of the disk cache, receive data to store to the disk cache, store the data to the cache resident partition at least initially, create tape-managed partitions in the disk cache, each of the tape-managed partitions being configured to store data that is subject to HSM, and manage the tape-managed partitions to have a size that is greater than a second minimum size and less than or equal to a total size of the disk cache less a size of all other partitions combined.

Abstract: Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes are provided. QOS data is collected for the plurality of storage volumes and includes a response time in which each of the plurality of storage volumes respond to an input/output (I/O) request. An expected range for future QOS data based on the collected QOS data is generated. The process then determines a deviation of each potential bully storage volume of a resource used by any victim storage volume, where the deviation of each bully storage volume is based on a number of current I/O requests (IOPS) that are processed by each potential bully storage volume, a forecasted value of TOPS and a predicted upper threshold TOPS value for each potential bully storage volume; and filters the potential bully storage volumes based on an impact of each potential bully storage volume.

Abstract: Disclosed aspects include management of a set of blocks in a storage system. A set of write requests is initiated to the set of blocks. In response to the set of write requests, a set of expiration metadata for the set of blocks is established. Based on the set of expiration metadata, an expiration event is detected. In response to detecting the expiration event, an expiration operation on the set of blocks is processed.

Abstract: A system and method can support smart buffer management in a distributed data grid. A buffer manager in the distributed data grid can provide a plurality of buffers in a buffer pool in the distributed data grid, wherein the plurality of buffers are arranged in different generations and each buffer operates to contain one or more objects. The buffer manager can prevent a garbage collector from directly recycling the memory associated with each individual object in the buffer pool, and can allow the garbage collecting of one or more objects in one or more buffers in a particular generation to be performed together.

Abstract: Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes are provided. QOS data is collected for the plurality of storage volumes and includes a response time in which each of the plurality of storage volumes respond to an input/output (I/O) request. The process determines an average of N collected QOS data points at any given time; and iteratively analyzes each QOS data point to detect if a step-up or a step-down function has occurred, where a step-up function represents an unpredictable increase in value of a data point and a step-down function is an unpredictable decrease in value of the data point. A subset of the N QOS data points based on when the step-up function or step-down function occurs is selected for analysis and an expected range for future QOS data based on the subset of the N QOS data points is generated.

Abstract: Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes from a storage operating system of a storage system are provided. A performance manager collects the QOS data from the storage operating system and the QOS data includes a response time in which each of the plurality of storage volumes respond to an input/output (I/O) request. An expected range for future QOS data is generated based on the collected QOS data. The QOS data is monitored for each storage volume for determining whether a current QOS data for each storage volume is within the expected range.

Abstract: A semiconductor memory device may include a memory cell array, and a program and verify circuit configured to perform a write operation on the memory cell array by repeating a plurality of program and verify operations. When the write operation is stopped after a first program operation is performed according to a first program condition, the PNV circuit may perform a first verify operation corresponding to the first program operation according to a first target value, after the write operation has resumed.

Abstract: A computer-implemented method for caching data on virtualization servers may include: 1) providing a virtualization server that executes at least one virtual machine on the virtualization server, 2) intercepting a data operation that includes both basic data and metadata, the data operation being requested by the virtualization server, 3) caching the basic data from the data operation on a solid state drive cache at the virtualization server, and 4) preventing the solid state drive cache from providing metadata from the data operation to the virtualization server. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.

Abstract: A memory access method is disclosed for computing n parallel threads that invoke one original execution module. The method includes determining a number k (n?1?k?1) of k mirror execution modules to be created based on the number of n parallel threads. The method includes determining a mapping policy F between n threads and k+1 execution modules. The k+1 execution modules refer to the original execution module and the k mirror execution modules. The method includes creating the k mirror execution modules and allocating individual private memory to each of the k mirror execution modules. The method includes executing the n parallel threads and making each thread invoke the execution module according to the mapping policy F, with each execution module only accessing its private memory pool. The method includes, after the n parallel threads are finishing executing, deleting the k mirror execution modules and releasing the resources.

Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.

Abstract: A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another.

Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method may include storing in a primary storage a plurality of list entries belonging to an ordered list. Free space in the primary storage may be monitored to determine whether a first predetermined condition related to the free space is met. In a secondary storage, a storage block of a predetermined size may be allocated for migration, when the first predetermined condition is met. A cursor may be provided pointing to a first list entry in the primary storage. One or more list entries may be selected at the cursor. The selected list entries may be migrated to the storage block while maintaining their order in the list.

Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method may include storing in a primary storage a plurality of list entries belonging to an ordered list. Free space in the primary storage may be monitored to determine whether a first predetermined condition related to the free space is met. In a secondary storage, a storage block of a predetermined size may be allocated for migration, when the first predetermined condition is met. A cursor may be provided pointing to a first list entry in the primary storage. One or more list entries may be selected at the cursor. The selected list entries may be migrated to the storage block while maintaining their order in the list.

Abstract: A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.

Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.

Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.

Abstract: In a memory control apparatus for issuing a command for a bank corresponding to a transfer request, the transfer request for the corresponding bank is stored. The column address of the transfer request stored at the first is compared with the column addresses of a plurality of subsequent transfer requests. It is determined based on the comparison result whether to issue a command with precharge or a command without precharge for the transfer request stored at the first. The determined command is issued.

Abstract: The present invention aims at improving the performance of a compression function in a storage system, and solves the prior art problem of having to decompress a whole compression unit even if a read request or a write request targets only a portion smaller than the compression unit, causing increase of overhead of decompression processing and elongation of processing time, and deteriorating performance. The present invention prevents unnecessary decompression processing and reduces the overhead of processing by suppressing the range of decompression processing to a minimum portion according to the relationship between the read/write request range and the compression unit.

Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.