Abstract: A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.

Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.

Abstract: A display apparatus includes a substrate, a light-emitting device provided on the substrate, a driving transistor device configured to control the light-emitting device, a first power supply line electrically connected to a source region of the driving transistor device, a conductive pattern electrically connected to a gate electrode of the driving transistor device, and a second power supply line electrically connected to the first power supply line, wherein the conductive pattern and the first power supply line constitute a first capacitor, and the conductive pattern and the second power supply line constitute a second capacitor, wherein the first capacitor and the second capacitor are connected in parallel.

Abstract: A thin-film transistor array substrate includes a substrate, a thin-film transistor disposed on the substrate, where the thin-film transistor includes a semiconductor layer including a channel area and a gate electrode overlapping the channel area, and a storage capacitor including a lower electrode disposed on the channel area and an upper electrode disposed to overlap the lower electrode, where an opening having a single closed curve-shape is defined through the upper electrode. On a plane, the upper electrode includes a first recessed portion and a second recessed portion, each exposing an edge of the lower electrode.

Abstract: A new and useful p-type oxide semiconductor with a wide band gap and an enhanced electrical conductivity and the method of manufacturing the p-type oxide semiconductor are provided. A method of manufacturing a p-type oxide semiconductor including: generating atomized droplets by atomizing a raw material solution containing at least a d-block metal in the periodic table and a metal of Group 13 of the periodic table; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base under an atmosphere of oxygen to form the p-type oxide semiconductor on the base.

Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.

Abstract: Provided are a thin-film transistor substrate that has enhanced electrical characteristics, such as off-current characteristics of a thin-film transistor, without increasing the number of mask processes, a display apparatus, and a method of manufacturing the thin-film transistor substrate. The thin-film transistor substrate includes: a semiconductor layer including a first conductive region, a second conductive region, and a first semiconductor region; a lower electrode disposed on the semiconductor layer and at least partially overlapping the first semiconductor region; and an upper electrode disposed on the lower electrode and at least partially overlapping the first semiconductor region, a first boundary between the first semiconductor region and the first conductive region coincides with an edge of the upper electrode, and a second boundary between the first semiconductor region and the second conductive region coincides with an edge of the lower electrode or an edge of the upper electrode.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.

Abstract: The disclosure relates to an organic light emitting display panel and an organic light emitting display device including the display panel. Specifically, the organic light emitting display panel includes a buffer layer on a first conductive layer, an active layer on or over the buffer layer, a first insulating film on or over the active layer and overlapping a part of an upper surface of the active layer, a second insulating film on or over the first insulating film and including a first contact hole exposing the part of the upper surface of the active layer, an electrode of an organic light emitting element contacting the active layer through the first and second contact holes, wherein an area in which the active layer and a second conductive layer contact is included in a node at which a reference voltage is applied to a driving transistor.

Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.

Abstract: The present invention provides a display panel and a display device. A first gate electrode and a first polar plate of a first thin film transistor are used to constitute a storage capacitor. At a same time, the first polar plate and a second gate electrode of a second thin film transistor are disposed in a same layer. Therefore, a gate insulation layer used to separate the first polar plate from the first gate electrode and the second gate electrode in layers can be omitted, so as to reduce a number of film layers in the display panel and a thickness of a film laminated structure, thereby reducing a complexity of a process flow of the display panel, and improving bending ability of the display panel.

Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.

Abstract: A transparent display device is disclosed, which may have high light transmittance in a non-display area as well as a display area, and may increase or maximize a light emission area in a non-transmissive area. The transparent display device comprises a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, anode electrodes provided in each of the plurality of subpixels over the substrate, a light emitting layer provided over the anode electrodes, a cathode electrode provided over the light emitting layer, a pixel power line provided over the substrate and extended in the display area in a first direction, and a common power line provided over the substrate and extended in the display area in the first direction. The display area includes a non-transmissive area provided with the common power line and the pixel power line, and a transmissive area provided between the common power line and the pixel power line.

Abstract: An embodiment of the present invention provides a display device including a substrate and a transistor on the substrate. The transistor includes: a lower layer having conductivity and including a body portion and a plurality of protrusions; an oxide semiconductor layer including a channel region, a first conductive region disposed at a first side of the channel region, and a second conductive region disposed at a second side of the channel region, where the second side is opposite the first side; a gate electrode overlapping the channel region in a plan view; a first electrode electrically connected to the first conductive region; and a second electrode electrically connected to the second conductive region. The plurality of protrusions protrudes from the body portion, and the body portion overlaps the channel region in the plan view.

Abstract: A display panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction and spaced apart from the first gate line in a second direction crossing the first direction; a first connection line extending in the second direction; and a second connection line extending in the second direction and spaced apart from the first connection line in the first direction, wherein a distal end of the first connection line overlaps the first gate line and is electrically connected to the first gate line, and wherein a distal end of the second connection line overlaps the second gate line and is electrically connected to the second gate line.

Abstract: An electrostatic discharge protection wiring is provided, and the electrostatic discharge protection wiring includes a gate signal line, a driving circuit, a gate connection line, and a source/drain. By disposing the bent gate connection line at an end of the gate signal line, the electrostatic discharge passes through the bent gate connection line to lose a part of current, thus reducing an effect of the electrostatic discharge to prevent bright spots at edges of panels caused by the weak electrostatic discharge.

Abstract: An organic light emitting display device may include a first thin film transistor including a first active layer formed of a first material and includes a first source region, a first channel region, and a first drain region, a first gate electrode and a first source electrode and a first drain electrode, a second thin film transistor including a second active layer formed of a second material and includes a second source region, a second channel region, and a second drain region, a second gate electrode, and a second source electrode and a second drain electrode, a light blocking layer overlapping a lower portion of the second active layer and formed on the same layer as the second capacitor electrode, and a first protrusion pattern and a second protrusion pattern disposed on the same layer as the first gate electrode and overlapping the light blocking layer.

Abstract: In the present disclosure, a photodiode structure is used as a photosensor in an array substrate. The semiconductor structure in the photosensor includes a N-type heavily doped amorphous silicon layer, an amorphous silicon layer, and a P-type heavily doped amorphous silicon layer, thereby realizing the integration of photosensors into large-sized devices, the enhancement of device sensitivity, and the reduction of costs.