Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.

Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

Abstract: A control amplifying circuit includes a power supply output circuit, an isolation control circuit and an amplifying circuit. The power supply output circuit is configured to receive a power supply switching signal, and select one preset voltage value from at least two preset voltage values according to the power supply switching signal to output as a preset power supply signal. The isolation control circuit is configured to receive a control command signal and the preset power supply signal, and generate an isolation control signal according to the control command signal. The amplifying circuit is configured to receive the isolation control signal and a signal to be processed, and amplify the signal to be processed based on the isolation control signal to obtain a target amplified signal.

Abstract: Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c

Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

Abstract: A semiconductor memory is provided. The semiconductor memory comprises a memory chip and a voltage regulation unit. The memory chip includes at least a storage array and the voltage regulation unit includes at least an operational amplifier. The voltage regulation unit is configured to convert an external input first voltage into a second voltage to be provided to a word line driver circuit associated with the memory chip. The first voltage is greater than the second voltage. According to the semiconductor memory provided, power consumption of the memory chip (or the semiconductor memory) is reduced and the second voltage provided to the word line driver circuit reaches a threshold voltage.

Abstract: A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.

Abstract: A word line driving circuit includes a driving circuit and a control circuit. The control circuit includes a control sub-circuit, a first switching sub-circuit and a second switching sub-circuit. The first switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a first power supply voltage, and a second terminal electrically connected with a third input terminal of the driving circuit. The second switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a second power supply voltage, and a second terminal electrically connected with the third input terminal of the driving circuit. The second power supply voltage is greater than a ground voltage.

Abstract: A semiconductor structure and a preheating method thereof are provided. The semiconductor structure includes: a storage chip; a temperature detection unit configured to detect a temperature of the storage chip before the storage chip initiates; and a control chip configured to: before the storage chip initiates, heat the storage chip and determine whether the temperature detected by the temperature detection unit reaches a specified threshold; and if the temperature reaches the specified threshold, control the storage chip to initiate. When the semiconductor structure provided in the present invention works at a low temperature, the storage chip may be heated to the specified threshold, thereby preventing an increase of the resistances on the bit line, the word line, and the metal connection line in the storage chip, and improving the performance of read/write operations of the memory.

Abstract: Various embodiments include a memory device that is capable of transferring both commands and data via a single clock signal input. In order to initialize the memory device to receive commands, a memory controller transmits a synchronization command to the memory device. The synchronization command establishes command start points that identify the beginning clock cycle of a command that is transferred to the memory device over multiple clock cycles. Thereafter, the memory controller transmits subsequent commands to the memory device according to a predetermined command length. The predetermined command length is based on the number of clock cycles needed to transfer each command to the memory device. Adjacent command start points are separated from one another by the predetermined command length. In this manner, the memory device avoids the need for a second lower speed clock signal for transferring commands to the memory device.

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

Abstract: A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Abstract: An operation method of a nonvolatile memory device includes receiving a first DQ signal representing a first data bit from an external device through a first DQ line and receiving a second DQ signal representing a second data bit from the external device through a second DQ line, and programming a first memory cell corresponding to the first DQ line and a second memory cell corresponding to the second DQ line such that the first memory cell has any one of an erase state and a first program state based on the first DQ signal and the second memory cell has any one of the erase state and a second program state based on the second DQ signal. A lower limit value of a threshold voltage distribution corresponding to the second program state is higher than a lower limit value of a threshold voltage distribution corresponding to the first program state.

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.