Abstract: A cellular array processor (10) for efficiently performing data dependent processing such as floating point arithmetic functions. One module (84) in the array processor (12) generates a signal applied to bus line (24) when all of the bits in a register (86) are zero. The signal on bus line (24) effects the shifting operation of a shift register (36) in a memory module (34) located on a different functional plane. Thus, the processing functions carried out in each elemental processor (26) can be made to depend on the value of data stored therein instead of being dictated solely by a simultaneous executed instruction from the control processor (14) as is the normal case.

Abstract: A variable-passband, variable-phase digital filter in which Q digital samples of a signal are entered through (Q-1) delay lines, to be delayed into q two-bit adjacent doublets. Weighting tables in read only memories are addressed by each doublet. Each weighting table includes the results of linear combinations of the weights of doublets composed of bits of the same order multiplied by multiplier coefficients which are smaller than unity. Each integral portion of a result found in a table is applied at the same time as the fractional portions of the other results provided by the other tables to the addressing inputs of a programmed memory containing binary words. Binary words are addressed in the prorammed memory by the integral and fractional portions of the results found in the weighting tables. Each binary word has a value equal to the linear combination of the corresponding values of the samples of the signal by the multiplier coefficients.