Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: There is provided a method for replacing a program stored in portable information terminal including a communication unit for transmitting to and receiving data from an external device, a memory unit for temporarily storing a new program and a utility program operating to carry out the replacement of a prestored program, which are received from the communication unit, and a program storage unit for storing the prestored program and replacing the prestored program with the new program. The method comprises the steps of receiving the new and utility programs via the communication unit from an external, storing the new and utility programs in the memory unit, and replacing the prestored program stored in the program storage unit with the new program, using the utility program. As described above, the program of a portable information terminal is replaced using a communication unit instead of an external card, so that the program can be replaced at low cost.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A system and method for controlling parameters in an electronic imaging device comprises a series of parameter storage locations coupled to the imaging device for containing parameter value sets, a set of parameter commands for controlling the parameter value sets, and a parameter manager device for executing the set of parameter commands to control the parameters in the electronic imaging device.

Abstract: A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information item is formed of two bytes, the DMA controller, while temporarily storing data received in odd-numbered order in a data-set adjusting register, controls block write of this together with data received in even-numbered order to the RAM. Due to this, access where data other than these data sets is intermixed is eliminated, even in a case where asynchronous word-unit access of the RAM is performed by the CPU.

Abstract: The present invention discloses an apparatus and a related method for achieving the purpose of improving the computer performance while inputting characters by using personal digital assistant (PDA) devices. The parallel port of the computer is connected with the PCMCIA (Personal Computer Memory Card International Association) card of the PDA device, and then a handshaking scheme is applied to establish a connection between the PC and the PDA device. After the connection has been successfully established, the input characters are transferred from the PDA device by parallel transformation without increasing the loading of the computer.

Abstract: The present invention is a standardized host-to-switch application program interface (API) for performing call control processing, capable of being customized to meet telecommunications application and network signalling protocol requirements. The universal API comprises one or more generic messages having programmable fields for transmitting commands, status, and data between the host application and the switch. The present invention further comprises a programmable telecommunication switch that provides a user with the ability to define a desired API protocol, either "standard" or custom in nature, for performing any desired switching functions. The present invention includes a protocol development environment which enables a user to define a separate finite state machine for each port provided by the switch.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer.

Abstract: An imaging system which incorporates a gate (which can be implemented either in hardware or software) for gating video signals to a host PC. The present invention allows fixed frame cameras to be used in applications which would otherwise require the host PC to have prohibitively large amounts of random access memory. However, by selecting predetermined frames of video data from a fixed frame output camera, the present invention simulates the effect of a variable frame rate camera.

Abstract: During start-up of an advanced configuration and power interface computer system, a resource lock value is read from nonvolatile memory. If the resource lock value indicates system resources are to be locked, possible configuration setting data associated with motherboard input-output devices, is not loaded into memory at a location known to the operating system. If the resource lock value indicates system resources are not to be locked, possible configuration setting data is loaded into memory at a location known to the operating system.

Abstract: An apparatus for data normalization includes a FIFO buffer for receiving input data words, an input register for receiving a first data word from the FIFO buffer, and a combinatorial circuit for transforming the first data word in the input register and a subsequent data word from the FIFO buffer into a normalized output data word. The apparatus utilizes two or more independent instruction streams to increase the processing speed of the apparatus.

Abstract: The present invention discloses a method for fetching the identifications of the SCSI (Small Computer Systems Interface) equipment even under the circumstances interrupted by ESD (Electro-Static Discharge). The fetch method samples the identification of an SCSI equipment plurality times, and then performs a classification scheme to those sampling values to search the sampling value that is most frequently appeared. The most frequently appeared sampling value is then treated as the identification of the SCSI equipment.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.