Abstract: A data communications system for supporting World Wide Web (WWW) database queries to enterprise level databases utilizes two server based programs. A first program retrieves and transmits a specified version of a specified form to an intermediate forms program. The second program has two modes of operation. In either mode, database queries to the enterprise level database are performed and results transmitted. However, in a first, standard, mode of operation, a specific version of a specific form is read from a forms database and transmitted to the requester along with the query response. In the second mode of operation, only the database query results are transmitted, along with a modified header that specifies the appropriate form. The corresponding forms are retrieved from a local forms database and merged with the query response before being displayed by a Web browser. Missing forms are requested from the Web forms program and cached for subsequent requests.

Abstract: A method of operating a multiple execution unit microprocessor in a software pipelined loop is disclosed. This method executes the loop body before the pipeline is fully initialized, thus replacing prolog instructions with additional loop iterations. The method has the potential to greatly reduce prolog size for many software pipelined loops. As a further aspect of the method, the loop results are insulated from any deleterious effects of loop body execution prior to full initialization—methods for accomplishing this are disclosed, including array overallocation, conditional execution of some loop body instructions, and register initialization.

Abstract: A central processing unit capable of solving a problem of a conventional one in that when a user tries to implement a cryptographic function unique to the user using the conventional central processing unit, it is necessary to connect an external operation unit through a bus, and this imposes a heavy development load on the user. The present central processing unit has, in an operation block performing operations based on a register file which operational instructions can directly refer to, an operation unit having a facility which provides the user with capability of setting its operational function.

Abstract: A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organised in an internal directed acyclic graph. A guarding is executed on successor instructions that each collectively emanate from a respectively associated single predecessor instruction. A subset of joined instructions that converge onto a single join/target instruction are then unconditionally joined. This is accomplished by letting each respective instruction in the subset of joined instructions be executed under mutually non-related conditions, specifying all operations with respect to a jump instruction, specifying all operations that must have been executed previously, and linking various basic blocks comprising subsets of successor instructions in a directed acyclic graph which allows parallel execution of any further subset of instructions contained therein.

Abstract: A method and article of manufacture, such as a magnetic disk containing computer instructions, for preventing a device driver from disabling an operating system during boot-up is provided. Fault tolerant booting software is provided in a computer having remote control software. The computer is able to provide video information to another remote computer in response to a user's input. The fault tolerant booting software interfaces with the computer's various device drivers, including, a video driver, keyboard driver, and a pointing device driver. The fault tolerant booting software attaches to identified device drivers to prevent a faulty driver filter from rendering the operating system inoperable for failing to load during a bootstrap routine. The method includes a step of restoring registry information after the fault tolerant booting software attaches the device filters to identified device drivers. Messages are also displayed to identify a faulty device driver.

Abstract: An information recording/reproducing apparatus that is an magneto-optical disk drive apparatus includes a disk controller that is connected to a SCSI controller and controls data transfer from/to a disk rotated by a spindle motor a cache memory temporarily storing data read from and written to the disk, a CPU controlling operation of respective blocks of the apparatus, a program storage that has an analyzing block for analyzing a file management area in the disk, and stores that operational programs for the CPU, and a read/write controller controlling record/reproduction of data to/from the disk. In this construction, since a part of D file management area in the disk is cached all the time at the time of read, data through a plurality of read from operations the boot sector, FAT1, and root directory are sent respectively from the cache memory without accessing the disk.

Abstract: A method for searching a non-tokenized text string for matches against a keyword data structure organized as a set of one or more keyword objects. The method begins by (a) indexing into the keyword data structure using a character in the non-tokenized text string. Preferably, the character is a Unicode value. The routine then continues by (b) comparing a portion of the non-tokenized text string to a keyword object. If the portion of the non-tokenized text string matches the keyword object, the routine saves the keyword object in a match list. If, however, the portion of the non-tokenized text string does not match the keyword object and there are no other keyword objects that share a root with the non-matched keyword object, the routine repeats step (a) with a new character. These steps are then repeated until all characters in the non-tokenized text string have been analyzed against the keyword data structure.

Abstract: The password input apparatus of the present invention comprises: a database for storing feature data of a previously registered master fingerprint and a password of an authorized user in a related manner; a camera for obtaining a fingerprint being inputted from the user's finger; an extractor for extracting feature data of the fingerprint; a controller for reading the password from the database based on the feature data extracted by the extractor; and an interface for outputting the password to another device.

Abstract: A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

Abstract: An apparatus and method for improving the execution of conditional branch instructions is provided. A static branch predictor makes predictions about the outcomes of branch instructions based upon a combination of the test type (such as jump on overflow, jump if negative, jump if zero, jump on carry, etc.) and the sign of the displacement of the branch instruction. If the test type of the branch instruction is one of a subset of test types from which the branch outcome can accurately be predicted solely from the test type, then the predictor makes such a prediction. Otherwise, the predictor makes a prediction based upon the sign of the displacement used to calculate the branch target address. In this case, backward jumps are predicted taken and forward jumps are predicted not taken.

Abstract: The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to read the word from the register array in each of the banks, a decoder to specify a bank corresponding to a result of decoding of remaining bits of the read address, and a multiplexer to select the word from the bank specified by the decoder so as to output the word to the read port.

Abstract: Apparatus and methods are described for reducing power consumption in a processor. The processor includes a source of microcode instructions, a microcode instruction decode circuit, control register latches and a clock gate control circuit that is coupled to the source of microcode instructions. The clock gate control circuit searches and picks groups of clock gate control signals for the latches that are the same value (state) as control signals form a previous cycle.

Abstract: A PC Card input/output device comprises a PC Card connector including a socket portion into which a PC Card can get inserted. The socket portion contains a switch which can be fully accommodated within a space defined by inner walls of the socket portion and a notch formed on a PC Card inserted if the upper and lower sides of the PC Card inserted are oriented in proper directions with respect to the socket portion, and which can be mechanically actuated so as not to prevent insertion of a PC Card if the upper and lower sides of the PC Card inserted are oriented in improper directions with respect to the socket portion, so that the switching state of the switch is changed. When the switch state of the switch is changed, a connection switching unit can change a connection between the plurality of connecting terminals of the PC Card connector and a plurality of terminals with which the connection has been set up, before the PC Card inserted is electrically connected to the PC Card connector.

Abstract: An apparatus for tracking pipeline resources of a processor involves fetching selected ones of the coded instructions and marking the fetched instructions with instruction metadata. The instruction metadata indicates a number of pipeline resources required by each instruction. The marked instructions are issued from the fetch unit and, using the instruction metadata, a count of a number of resources committed to issued instructions in the execution pipelines is maintained. When it is determined that the number of resources committed to issued instructions exceeds a preselected maximum and instructions are prevented from issuing from the fetch unit. As each instruction is retired, the instruction metadata is used to determine a number of resources released by retirement of the issued instruction.