Abstract: A transmit-receive station connected to a high speed ring bus carrying data signals that may be received from and sent to each station on the ring bus has two sources of transmit clocking signals. One source is based on the frequency and phase of data signals received on the ring bus from another station and the other source is a local crystal oscillator having essentially the same frequency as the first source but in an indeterminate phase. When changing the source of clocking signals for transmission of data originating at the station, bit slippage may be minimized by providing the local oscillator output signal in four phases and using the phase most nearly aligned with the other clocking signal when the change is made.Control of access to transmit by a station employs a token having a message field of seven bits and a access control bit.

Abstract: A communications system has a plurality of stations (S.sub.1, S.sub.2 . . . S.sub.N) interconnected by a pair of lines (10,11) so that one line (10) permits the stations (S.sub.1, S.sub.2 . . . S.sub.N) to transmit in one direction and the other line (111) permits transmission in the other direction. Frames each having a control field and a data field pass down the lines (10,11) and each station (S.sub.1, S.sub.2 . . . S.sub.N) can write a packet of data to any frame in which the data field is empty. This is signalled by a busy bit in the control field. The stations (S.sub.1, S.sub.2 . . . S.sub.N) are arranged to write data packets in cycles. The commencement of such a cycle for writing to signals on one line (10,11) is determined by a signal on the other line (11,10). That signal may be constituted by a suitable reset bit in the control field of a frame. Preferably, once the cycle of a station (S.sub.1, S.sub.2 . . . S.sub.

Abstract: A multiprocessor system is formed of a total of R.sup.n digital processors connected for mutual communication by unidirectional data lines. Each processor is connected for sending data to R other processors, and designating the address of an arbitrary processor as (P.sub.1 P.sub.2, . . . P.sub.i, . . . P.sub.n), the addresses of respective ones of these R processors are determined by executing a one digit right shift (or left shift) of that arbitrary processor address and changing a specific digit P.sub.i of that address to each of a set of values extending from 0 to (R-1).