Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the semiconductor device, command the semiconductor device to activate a feature not included in the first set of features to cause the semiconductor device to provide a second set of features, generate a second stock keeping unit for the semiconductor device, and associate the second stock keeping unit with the semiconductor device and the second set of features to be provided by the semiconductor device.

Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.

Abstract: In a general aspect, input data for a computer process are preprocessed by a preprocessor unit that includes a quantum processor. In some aspects, a preprocessor unit obtains input data for a computer process that is configured to run on a computer processing unit. Randomized parameter values are computed for variable parameters of a quantum logic circuit based on the input data. A classical processor in the preprocessor unit computes the randomized parameter values from the input data and a set of random numbers. A quantum processor in the preprocessor unit produces quantum processor output data by executing the quantum logic circuit having the randomized parameter values assigned to the variable parameters. Preprocessed data generated based on the quantum processor output data are then provided as the input for the computer process configured to run on the computer processing unit.

Abstract: A data storage system may connect a host to a device and a hardware module that are utilized to satisfy at least one host-generated data access request to the device. A portion of the device is set as dormant by the hardware module prior to identifying an origin of the device with the hardware module during the satisfaction of the at least one host-generated data access request. In response to the identified origin, the previously dormant portion of the device is activated and subsequently utilized to execute a task assigned by the hardware module.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: Unified management, automation and interoperability of business and device processes utilizing components of a metadata-driven computing system on any device and/or across difference devices. In an embodiment, a I/O processor on a device receives an input dataset, wherein the input dataset may be a messages dataset received from a message broker. The I/O processor accesses one or more instructions datasets nested within a state dataset to process each row in the input dataset. Processing of the input dataset by the I/O processor updates the state of the state dataset and may output one or more datasets, wherein an output dataset may be a messages dataset sent to a message broker to send to a computing system for processing. A messages dataset may comprise one or more messages, wherein a message may comprise one or more events, queries, or query results for processing by a computing system.

Abstract: A method includes protecting a boot sequence of a processing device by incrementing a counting value generated by a monotonic counter, then a first time period after the beginning of the boot sequence, comparing, by the protection circuit, the counting value with a first reference value, and, if the counting value is smaller than the first reference value, changing, by the protection circuit, the counting value to the first reference value.

Abstract: The present invention is a system for providing power and controlling a plurality of ethernet devices as described. A driver, wherein the driver provides for the control of the system; a plurality of sensors, wherein the plurality of sensors collect sensor specific data and are in communication with the driver; a Power over Ethernet (POE) switch, wherein the POE switch is in communication with the plurality of sensors; a plurality of fixtures in communication with the driver and the POE switch, wherein the plurality of fixtures are light sources; and a local power source, wherein the local power source is in communication with the POE switch.

Abstract: An information handling system includes a management controller that may determine average power consumption of a processor, and determine average power measurement at a power supply unit. If the average power consumption of the processor does not match the average power measurement at the power supply unit, then the system may calibrate the average power consumption of the processor to match the average power measurement at the power supply unit.

Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; a power controller to control power consumption of the plurality of cores, the power controller to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. Other embodiments are described and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

Abstract: An apparatus (1) provided to connect at least one device (2) to a power distribution system (3), said apparatus (1) comprising a human machine interface, HMI, (4) having elements to interact with the apparatus (1), wherein the human machine interface elements (11,12) are adapted to display and/or to adjust setting values of operation parameters of the at least one connected device (2), wherein access to one or more human machine interface elements is restricted by at least one access restriction mechanism of said apparatus (1) to enhance the operation security of the at least one device (2) connected via said apparatus (1) to said power distribution system (3) and/or to enhance the operation security of the apparatus (1) and/or of the power distribution system (3).

Abstract: An information processing apparatus includes a first CPU, a second CPU, a first nonvolatile memory that stores a boot program to be executed by the first CPU at a time of start-up, and a second nonvolatile memory that stores a first boot program and a second boot program for verifying a program. The first CPU determines whether or not a verification method is set in the first nonvolatile memory, and if not, the first CPU executes the first boot program, and writes the setting of the verification method to the second nonvolatile memory. If the verification method is set, the first CPU executes the second boot program in accordance with the setting, and when the processing of the second boot program is normally ended, the second CPU starts up the information processing apparatus.

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

Abstract: A node interconnection apparatus includes a computing node and a resource control node, and a device interconnection interface connecting the two. Each of the computing node and the resource control node includes a processing unit and a storage unit, and the resource control node further includes a resource interface for connecting with a network storage device. The resource control node manages storage resource of the network storage device, and when the computing node needs to start up, the resource control node obtains operating system startup information from the network storage device and provides the information to the computing node. The computing node can start up without the need for storing startup information locally.

Abstract: A log generated over a time period of garbage collection cycles of a microservice is reviewed. The log includes garbage collection events and pause times for each event. A determination is made that a threshold number of consecutive garbage collection events has been reached where each consecutive event had a pause time exceeding a threshold pause time. Upon the determination, a change is made to a configuration file associated with the microservice to reduce the pause times for a next time period. Once the microservice enters an idle state, a command is generated to restart the microservice for the change in the configuration file to take effect.

Abstract: A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.

Abstract: A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

Abstract: Methods, systems, and computer-readable storage media for receiving data representative of a physical entity, generating an initial knowledge graph representative of a process that is executed by the physical entity based on the data, enriching the initial knowledge graph to provide a process aware energy consumption (PAEC) digital twin of the process as an enriched knowledge graph, providing at least two permutations based on the PAEC digital twin, executing analytics at least partially based on the at least two permutations to provide one or more recommendations, and executing at least one recommendation to optimize energy consumption of the physical entity.