Abstract: A method of testing phase locked loops (PLL) and a testing circuit comprising the steps of applying a normal stimulus signal whose frequency is within the lock range of the PLL to the input of the PLL, substituting the normal input stimulus with an alternative signal derived from an internal feedback of the PLL, adding or deleting one or more cycles from the alternative signal and observing the response of the PLL to the alternative signal. Variations of the method allow for determining Gain-Bandwidth product, lock range, lock time, Bit Error Rate, Jitter and other parameters which can then be compared with predetermined values to determine whether the PLL is properly functional.

Abstract: A phase shifter system includes a number of gates 40, 41 for receiving a reference clock and a number of gates 30-33 for receiving a predicted desired phase. The reference clock is manipulated by latches 43-46 and further gates 48, 49 so as to produce quadrature derivatives and these are connected across the resistor chain R1-R9 to produce multilevel waveforms, the steps being selected by selector 36 connected to the resistor nodes under the control of the predicted phase information from gates 30-33. Filtering and reshaping via comparator 50 provides an output clock pulse of desired phase. The output clock can be used to provide phase control in a transmission/reception system on a communications network.