Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

Abstract: Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Abstract: An electrical device is provided that includes at least one contact surface and an interlevel dielectric layer present atop the electrical device. The interlevel dielectric layer may include at least one trench to the at least one contact surface of the electrical device. A liner of tantalum or tantalum nitride can be present on sidewalls of the trench structure and a base surface of the trench provided by the contact surface of the electrical device. A copper fill promoting liner that includes at least one ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), molybdenum (Mo), and copper (Cu) may be in direct contact with the liner of tantalum or tantalum nitride. A copper containing metal that fills the at least one trench and is present directly on the copper fill promoting liner.

Abstract: A semiconductor device includes a radiation plate having a rear surface roughened by a plurality of dents that overlap with each other; a laminated substrate provided on a front surface of the radiation plate and including an insulating plate, a circuit board provided on a front surface of the insulating plate, and a metal plate provided on a rear surface of the insulating plate; a semiconductor chip provided on the circuit board; a radiator; and a heat radiating material retained between the rear surface of the radiation plats and the radiator. The plurality of dents that roughen the rear surface of the radiation plate provides the rear surface with an arithmetic average roughness ranging from 1 ?m to 10 ?m, and each of the dents has a maximum dent depth ranging from 12 ?m to 71.5 ?m, and a dent width ranging from 0.17 mm to 0.72 mm.

Abstract: The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

Abstract: The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: A semiconductor device includes a semiconductor element, a substrate formed with a recess in a main surface, a conductive layer formed on the substrate and electrically connected to the semiconductor element, and a sealing resin covering the semiconductor element. The substrate is made of an electrically insulative synthetic resin. The recess has a bottom surface on which the semiconductor element is mounted, and an intermediate surface connected to the main surface and the bottom surface. The bottom surface is orthogonal to the thickness direction of the substrate. The intermediate surface is inclined with respect to the bottom surface.

Abstract: Methods for forming an OLED device are described. An encapsulation structure having organic buffer layer and an interface layer disposed on the organic buffer layer sandwiched between barrier layers is deposited over an OLED structure. In one example, an OLED device includes a first barrier layer disposed on a region of a substrate having an OLED structure disposed thereon, a fluorinated buffer layer including a polymer material containing fluorine disposed on the first barrier layer, an interface layer including the polymer material on the fluorinated buffer layer, and a second barrier layer disposed on the interface layer.

Abstract: A display panel is disclosed, which includes: a substrate with a first surface; a first conductive line with a first inclined surface, a second conductive line with a second inclined surface, a third conductive line with a third inclined surface and a fourth conductive line with a fourth inclined surface respectively disposed on the first surface of the substrate, wherein the first conductive line intersects the second conductive line and the fourth conductive line, and the third conductive line intersects the second conductive line and the fourth conductive line, wherein an angle included between the first surface and the first inclined surface or an extension surface thereof of the first conductive line is different from an angle included between the first surface and the third inclined surface or an extension surface thereof of the third conductive line.

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

Abstract: A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through opening of a stiffener and a second routing circuitry positioned outside of the through opening of the stiffener and electrically connected to the first routing circuitry and a vertical connecting element of the stiffener. The mechanical robustness of the stiffener and the anti-warping controller can prevent the assembly from warping, whereas the vertical connecting element of the stiffener provides electrical connection between two opposite sides of the stiffener. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener.

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

Abstract: A device includes a carrier having a plurality of cavities, a micro-electro-mechanical system (MEMS) substrate bonded on the carrier, wherein the MEMS substrate comprises a first side bonded on the carrier, a moving element over a bottom electrode, wherein the bottom electrode is formed of polysilicon and a second side having a plurality of bonding pads and a semiconductor substrate bonded on the MEMS substrate, wherein the semiconductor substrate comprises a top electrode and the first moving element is between the top electrode and the bottom electrode.

Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract: A device includes a carrier having a plurality of cavities, a micro-electro-mechanical system (MEMS) substrate bonded on the carrier, wherein the MEMS substrate comprises a shielding layer on the carrier and coupled to ground, a plurality of vias coupled between the shielding layer and a bottom electrode of the MEMS substrate and a moving element over the bottom electrode and a semiconductor substrate bonded on the MEMS substrate, wherein the semiconductor substrate comprises a top electrode, and wherein the moving element is between the top electrode and the bottom electrode.

Abstract: A display unit includes a display region, a peripheral region, an insulating layer, a separating groove, and a sealing section. A plurality of pixels are disposed in the display region. The peripheral region is provided on outer edge side of the display region. The insulating layer extends from the display region to the peripheral region. The separating groove is provided in the peripheral region and separates the insulating layer into an inner peripheral portion and an outer peripheral portion. The sealing section is provided in the outer peripheral portion of the insulating layer and seals the display region. The separating groove has a width that is narrower as a distance is larger from an outer end of the display region to an outer end of the sealing section, and is wider as the distance is smaller.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.

Abstract: A method for vias and monolithic interconnects in thin-film optoelectronic devices (100, 200) wherein at least one line segment via hole (163, 165, 165?, 167) is formed by laser drilling and passes through front-contact layers (150, 152, 154, 156, 158) and semiconductive active layer (130), and wherein laser drilling causes forming a CIGS-type wall (132, 134, 136, 138) of electrically conductive permanently metalized copper-rich CIGS-type alloy at the inner surface (135) of the via hole, thereby forming a conductive path between at least a portion of front-contact and a portion of back-contact layers (120, 124, 126, 128, 129), forming a bump-shaped raised portion (155) at the surface of the front-contact layer, forming a raised portion (125, 127, 127?) of the back-contact layer, and optionally forming a raised portion of copper-rich CIGS-type alloy (155?) covering a portion of the front-contact layer (150). A thin-film CIGS device comprises at least one line segment via hole obtainable by the method.