Patents Examined by Thein F Tran
  • MOS device with varying trench depth
    Patent number: 7948029
    Abstract: A semiconductor device includes a drain, an epitaxial layer overlaying the drain, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, the active region contact trench having a varying contact trench depth, and an active region contact electrode disposed within the active region contact trench.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 24, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Xiaobin Wang
  • Crown capacitor using a tapered etch of a damascene lower electrode
    Patent number: 6222219
    Abstract: A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, David E. Kotecki