Abstract: An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity type. The transistor further includes a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions. A number of charge balancing structures are integrated with the semiconductor region so as to extend parallel to the current flow. In a blocking state, the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

Abstract: To reduce electric current concentration and electric field concentration in junction parts even in the case of miniaturization, and to achieve triggering at low voltage, an ESD protection apparatus is installed between an input terminal of a semiconductor integrated circuit chip and a CMOS transistor. The ESD protection apparatus includes a trigger element having diodes which are broken down by overvoltage applied to the input terminal and an ESD protection element including vertical bipolar transistors for discharging the accumulated electric charge of the input terminal by being electrically discharged owing to the breakdown of the diodes.

Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.

Abstract: A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.

Abstract: In a method for forming a silicon-on-insulator FET providing a contact to be given a fixed potential to a substrate, substrate-biasing between an SOI transistor and the silicon substrate is performed via a plug. As a result, the contact hole for the substrate-biasing does not need to pass through an insulating layer, a silicon layer, and an interlayer insulating layer. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can be implanted to the surface of the substrate via the contact hole for substrate biasing. As a result, contact holes for substrate-biasing can be formed without the contact holes for substrate-biasing causing an opening fault.

Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

Abstract: Provides a semiconductor that enables to suppress deformation of the opening portions due to thermal expansion and contraction and to improve production yield and reliability wiring, and a method of fabricating the same. A first conductive layer and a second conductive layer are formed on a substrate. An insulation film is formed on upper surfaces of the first and second conductive layers and has a plurality of first opening portions to expose either the first or second conductive layer and a plurality of second opening portions to expose neither the first nor the second conductive layer. The second opening portions are formed between the first opening portions. A third conductive layer formed on an upper surface of the insulation film and has an electrical connection between the first and second conductive layers through the first opening portions.

Abstract: A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to the first surface of the stiffener ring. A second substrate of a second chip package is secured to the second surface of the stiffener ring. The first substrate is connected to the second substrate through a plurality of solder balls. The heat generated in the first chip package and the second chip package is dissipated by the heat sink. The first chip package and the second chip package are fixed by the stiffener ring to eliminate warpage of the first chip package and the second chip package, thereby assuring the electrical transmission of the product.

Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

Abstract: A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.

Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.

Abstract: The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

Abstract: A semiconductor device has a semiconductor chip with a periphery and an IC organized in a core portion and a peripheral portion. The IC has a top level of interconnecting metal traces (510) from the peripheral portion to the core portion; the traces are covered by an insulating overcoat (520) which has peripheral windows to expose bond pads. The circuit further has at least one level of metal lines (511) on top of the insulating overcoat; the lines lead from the chip periphery towards the chip core, wherein each line (511) is substantially parallel to one of the traces (510) underneath the insulating overcoat and vertically aligned therewith. After assembling the chip onto a leadframe with segments (504), bonding wires (502) connect the bond pads (510a) and the metal lines (511a) with the segments.

Abstract: A method of fabricating a semiconductor device, includes depositing, on a semiconductor substrate, a gate insulating film, a polycrystalline or amorphous silicon film, a silicon nitride film and a silicon oxide film sequentially, patterning a resist for forming a plurality of trenches on an upper surface of the substrate so as to have opening widths differing from each other, etching the silicon oxide film and the silicon nitride film formed on the substrate by an reactive ion etching (RIE) process with the resist serving as a mask, and etching the polycrystalline or amorphous silicon film, the gate insulating film and the substrate by the RIE process with the etched silicon oxide film and silicon nitride film serving as a mask using reactive plasma including a halogen gas, fluorocarbon gas, Ar and O2, thereby simultaneously forming the trenches with opening widths differing from each other.

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Abstract: Disclosed herein is a flip-chip type nitride semiconductor light emitting diode. The light emitting diode comprises an n-type nitride semiconductor layer formed on a transparent substrate and having a substantially rectangular upper surface, an n-side electrode which comprises at least one bonding pad adjacent to at least one corner of the upper surface of the n-type nitride semiconductor layer, extended electrodes formed in a band from the bonding pad along four sides of the upper surface of the n-type nitride semiconductor layer and one or more fingers extended in a diagonal direction of the upper surface from the bonding pad and/or the extended electrodes, an active layer and a p-type nitride semiconductor layer sequentially stacked on a region of the n-type nitride semiconductor layer where the n-side electrode is not formed, and a highly reflective ohmic contact layer formed on the p-type nitride semiconductor layer.