Abstract: A Micro-Electro-Mechanical System (MEMS) device includes a substrate, a packaging component provided on the substrate and a MEMS component provided inside the packaging component and on the substrate. The device further includes a sealing component. The sealing component is provided on the substrate and/or the packaging component, for preventing an external small molecule from contacting with the MEMS component.

Abstract: A device may include a filter array disposed on a substrate. The filter array may include a first mirror disposed on the substrate. The filter array may include a plurality of spacers disposed on the first mirror. A first spacer, of the plurality of spacers, may be associated with a first thickness. A second spacer, of the plurality of spacers, may be associated with a second thickness that is different from the first thickness. A first channel corresponding to the first spacer and a second channel corresponding to the second spacer may be associated with a separation width of less than approximately 10 micrometers (?m). The filter array may include a second mirror disposed on the plurality of spacers.

Abstract: A radiation-emitting component includes a semiconductor layer sequence including first and second semiconductor layers, and an active region and is arranged between the first and second semiconductor layers, first and second electrodes electrically connect to the first and second semiconductor layers, a semiconductor layer sequence generates electromagnetic radiation depending on a current flow between the first and second electrodes, a driver field-effect transistor includes at least one driver gate and at least one driver channel, the second electrode and the driver channel electrode separately electrically connect to the driver channel and the driver gate electrode electrically connects to the driver gate, and the driver field-effect transistor is configured to control a current flow between the driver channel electrode and the second electrode through the driver channel and thereby the current flow between the first and second electrodes, depending on a voltage applied to the driver gate electrode.

Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

Abstract: A semiconductor device including a device substrate and a readout circuit substrate. The device substrate includes a device region and a peripheral region. In the device region, a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked. The peripheral region is disposed outside the device region. The readout circuit substrate faces the first semiconductor layer with the wiring layer in between, and is electrically coupled to the first semiconductor layer through the wiring layer. The peripheral region of the device substrate has a junction surface with the readout circuit substrate.

Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.

Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

Abstract: A semiconductor device comprises: a cell region that includes a semiconductor element; an outer peripheral region that surrounds an outer periphery of the cell region; a substrate that has a front surface and a back surface, and is made of a semiconductor of a first or second conductivity type; a first conductivity layer that is formed on the front surface of the substrate and made of the semiconductor of the first conductivity type having a lower impurity concentration than impurity concentration of the substrate; a first electrode that is provided on an opposite side of the substrate across the first conductivity layer, the first electrode being provided in the semiconductor element; and a second electrode that is placed toward the back surface of the substrate, the second electrode being provided in the semiconductor element.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose an etch stop layer in the preliminary pattern; forming a dielectric layer on a sidewall of the opening; performing a first etching process to penetrate the etching stop layer and form a hole; performing a second etching process to expand a portion of the hole in the substrate; removing the dielectric layer; and depositing a conductive preliminary pattern on the sidewall of the opening and in the hole.

Abstract: In a method of manufacturing a transparent display device, a substrate including a pixel region and a transmission region may be provided. A first electrode may be formed on the substrate in the pixel region, and a display layer may be formed on the first electrode. A second electrode facing the first electrode may be formed on the display layer, and a capping structure including a first capping layer and a second capping layer may be formed on the second electrode. The first capping layer may be formed on the second electrode in the pixel region and a first region of the transmission region by using a mask that has an opening, the mask may be shifted, and the second capping layer may be formed on the second electrode in the pixel region and a second region of the transmission region by using the shifted mask.

Abstract: Methods and apparatus for forming a conformal SiOC film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a steam annealing process to decrease the nitrogen content, increase the oxygen content and leave the carbon content about the same. The annealed film has one or more of the wet etch rate or dielectric constant of the film.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

Abstract: An image sensor includes a plurality of pixels, at least one of the pixels comprising: a photodiode configured to generate charges in response to light; and a pixel circuit disposed on the substrate, and including a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

Abstract: A display device includes a bottom substrate including a display area and a non-display area around the display area, a thin film transistor region in the display area, the thin film transistor region including a plurality of thin film transistors and a plurality of pixel electrodes each electrically connected to a respective one of the thin film transistors, a top substrate facing the bottom substrate with the thin film transistor region therebetween, a seal in the non-display area to surround the thin film transistor region, the seal being configured to bond the bottom substrate to the top substrate, a wiring group between the seal and the bottom substrate, the wiring group including a plurality of conductive lines spaced apart from each other by a predetermined interval, and a light-scattering layer between the seal and the top substrate, the light-scattering layer including light-scattering particles.

Abstract: A cleaving system employs a shaper, a positioner, an internal preparation system, an external preparation system, a cleaver, and a cropper to cleave a workpiece into cleaved pieces. The shaper shapes a workpiece into a defined geometric shape. The positioner then positions the workpiece such that the internal preparation system can generate a separation layer at the cleaving plane. The internal preparation system focuses a laser beam internal to the workpiece at a focal point and scans the focal point across the cleaving plane to create the separation layer. The external preparation system scores the external surface of the workpiece at a location coincident with the separation layer. The cleaver cleaves the workpiece by propagating the crack on the external surface along the separation layer. The cropper shapes the cleaved piece into a geometric shape as needed.

Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.

Abstract: A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.

Abstract: A semiconductor device include a semiconductor substrate, a first trench electrode formed in the semiconductor substrate and having a first portion, a second trench electrode formed in the semiconductor substrate having a second portion facing the first portion, a floating layer of a first conductivity type formed around the first and second trench electrodes, a drift layer of a second conductivity type connected to the floating layer of the first conductivity type and formed between the first and second trench electrodes, an impurity layer of the first conductivity type connected to the drift layer of the second conductivity type and formed between the first and second trench electrodes, and a floating layer control gate having a portion located at least above the impurity layer of the first conductivity type.