Abstract: An IO cell for providing a transmission path for a binary signal. The IO cell includes an IO buffer for amplifying the binary signal. A programmable delay element is electrically connected to the IO buffer such that the binary signal transmits from the programmable delay element to the IO buffer. The delay element is responsive to “n” number of programmable binary bits to selectively delay transmission of the binary signal by a set of predetermined delay time ranges. An IO pad is connected in series with the IO buffer and the programmable delay element.

Abstract: A controller for initiating an insertion of one or more wait states on a signal bus includes registers, AND logic circuits, a counter and a OR logic circuit. One register is for connecting to a signal bus and receiving therefrom a clock signal and in response thereto receiving and latching an address strobe signal to provide a latched address strobe signal. One AND logic circuit is for receiving the latched address strobe signal, connecting to the signal bus and receiving therefrom an address write signal and a chip select signal and logically. ANDing the latched address strobe signal, the address write signal and the chip select signal to provide a first ANDed signal. Another register is for receiving a second clock signal and in response thereto receiving and latching the first ANDed signal to provide a first latched ANDed signal. Another AND logic circuit is for receiving and logically ANDing the first latched ANDed signal and a decoded address signal to provide a second ANDed signal.

Abstract: A CPU includes a register for setting a clock frequency and a frequency divider. The CPU sets an internal clock by frequency-dividing an externally supplied fundamental clock. A set of data set in the frequency setting register is selected through a setup menu displayed on a display unit. Of the data constituting the selected set, a default value is set in the register. When a predetermined key operation designating a frequency switching operation is detected by a detection circuit, the CPU updates the data set in the frequency setting register in accordance with the key operation, thereby changing the operating speed.

Abstract: Automatic detection of the activities of a user of a data processing system is provided by the use of an Activity Event Detection Process, an Activity Detection Process, and an Interrogator Process. The Activity Event Detection Process detects events indicating user activity. The Activity Detection Process evaluates the user activity indicating events to determine the activity of a user. The Interrogator Process provides an interface to a requesting user and formulates appropriate queries to be sent to one or more Activity Detection Processes.

Abstract: Apparatus and method for performing an application-defined operation on data as part of a system-defined operation on the data. The apparatus and method are embodied in a distributed transaction processing system in which processes running on component systems which may be heterogeneous interact according to the client-server model. In the apparatus and method, a type is associated with the data and application-defined operations which are part of certain system-defined operations are defined for each type. The system-defined operations which the application-defined operations are part of include allocation, reallocation, and deallocation of buffers and sending buffers between clients and servers using remote procedure calls. In the allocation and reallocation operations, the application-defined operation is initialization; in the deallocation operation, it is uninitialization.

Abstract: A stellate store and broadcast network with collision avoidance comprising a plurality of terminal devices, a central station for collectively relaying data packets issuing from the terminal devices and broadcasting them to the relevant terminal devices, and bidirectional communication channels interposed one each between the terminal devices and the central station, which stellate store and broadcast network is characterized by further incorporating therein reception memories disposed one each at the terminal interfaces of the central station, control circuits for monitoring the statuses of the reception memories, and means for broadcasting the data read out of the reception memories to all the reception lines.

Abstract: An electronic circuit board electrically connected to other circuits of a data processing system by means of a bus, may be removed and re-inserted in the system without the necessity of disabling other circuits connected to the bus. A latch actuated switch provides a control signal in anticipation of circuit board removal. The control signal activates a finite state machine which seizes control of the bus after completion of any current bus communications and stops the generation of clock pulses normally required in bus communications. When contact is physically broken between the board and its corresponding connector, the finite state machine restores the bus clock pulses and relinquishes control of the bus. When a board is to be inserted in an open connector, contact between the board and the connector is sensed by the finite state machine which causes the bus to be seized and the bus clock pulses to be temporarily inhibited.

Abstract: A message storage system (104) deletes leading silence from messages to be stored therein. Voice messages are converted to digital signals and stored as data blocks in a digital memory (601). Voice signals are detected in messages to be stored and a voice present signal is generated during periods of time when voice signals are detected. The memory is set to a starting location after the storage of each group of four data blocks of a message until a voice present signal is generated, thereby deleting leading data blocks which do not contain voice signals.

Abstract: A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group.

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.