Abstract: A compensation circuit comprising: a first source having an output; a second source having an output; a first transistor having a first current terminal coupled to the output of the first source, a second current terminal coupled to ground and a first control terminal connected to the first current terminal; a second transistor having a second control terminal, a third current terminal coupled to the output of the second source and a fourth current terminal coupled to ground; a first resistor connected between the first control terminal and the second control terminal; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor connected to the second control terminal.

Abstract: A power converter includes a switched-capacitor circuit that forms different capacitor networks out of a set of capacitors. It does so in a way that avoids losses that can arise when capacitors are connected together.

Abstract: A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.

Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.

Abstract: Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.

Abstract: A semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.

Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: An electronic control system provides selectable path operation, such as linear and pulse-width modulated (PWM) operation and provides path transition management to improve operation. The system supplies a current or a voltage to a load in response to an input signal or value and includes an output driver, and multiple selectable control paths. The system includes a control circuit that selects between the first control path and the second control path in response to a path selection indication to drive the output driver. The system may include an evaluator that determines the path selection indication in conformity with an amplitude and a slew rate of the input. One or all of the control paths may have a response time to changes in the input signal or value, and the control circuit may delay switching from the second control path to the first control path to compensate for the response time.

Abstract: Example embodiments include an apparatus with a buffer amplifier having an output node. A first switchable unidirectional current path is provided between the output node and a capacitor, the first path allowing current flow from the capacitor to the output node. A second switchable unidirectional current path is provided between the output node and the capacitor, the second path allowing current flow from the output node to the capacitor. Comparator circuitry is provided that operates to open the first path if the capacitor voltage is above an upper threshold and to open the second path if the capacitor voltage is below a lower threshold. The capacitor voltage may be read by an analog-to-digital converter.

Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.

Abstract: In accordance with an embodiment, a linear voltage regulator includes: a first transistor coupled between a first input terminal and an output terminal, the first input terminal adapted to receive a first voltage, and the output terminal adapted to provide a regulated voltage; a second transistor coupled between a second input terminal and the output terminal, the second input terminal adapted to receive a second voltage; and an amplifier of a difference between a third voltage proportional to the voltage at the output terminal and a reference voltage, an output of said amplifier being selectively coupled to a control terminal of the first transistor and to a control terminal of the second transistor, the amplifier being supplied by a fourth voltage corresponding to a highest voltage of the first voltage and the second voltage.

Abstract: A method of controlling a wireless power transmitter to detect a foreign object can include in response to a wireless power receiver being placed in a charging area of the wireless power transmitter, determining a current peak frequency; collecting a communication error count related to communication between the wireless power transmitter and the wireless power receiver; determining a reference frequency for detecting the foreign object based on a reference peak frequency received from the wireless power receiver; and determining that the foreign object is present within the charging area based on the current peak frequency, the communication error count and the reference frequency.

Abstract: A charged particle acceleration device, which eliminates the need for repeating alignment adjustment even in the case of repeating installation of the controllers, is provided, and a method for adjusting the same is provided. A charged particle acceleration device 10A includes: controllers 15,15a,15b,15c configured to control a beam trajectory 12 of charged particles that pass through a duct 11 to be inserted through the controllers 15; and a stage 20 that is supported by a frame 16 fixed to a base and reversibly moves the controllers 15 in a direction of intersecting the beam trajectory 12.

Abstract: An electronic device includes a controller, a clock generator, a first operation interface and a first functional unit. The controller generates a first clock enable signal, and then generates a first operation instruction. The clock generator generates a first clock according to the first clock enable signal. The first operation interface generates a first power supply signal according to the first clock, and translates the first operation instruction into a first operation signal. The first functional unit is enabled according to the first power supply signal, and starts to operate according to the first operation signal.

Abstract: A system for emitting light (such as a luminaire) includes a first light emitting diode (LED) string and a first LED driver that is electrically connected in parallel to the first LED string. The system also may include a second (or more) LED string(s), each associated with an additional LED driver. One-way conductors and normally-open switches are used so that if one LED driver fails, the remaining LED driver(s) will deliver power to the failed driver's LED string so that the light remains operational, but with a reduced brightness.

Abstract: A device operative to transfer power and communicate wirelessly includes a drive-sense circuit (DSC), memory that stores operational instructions, and processing module(s). The DSC generates a drive signal based on a reference signal and provides the drive signal to a first coil via a single line and via a resonating capacitor, and simultaneously senses the drive signal via the single line, to facilitate electromagnetic coupling to a second coil to transfer power wirelessly to another device. The DSC also detects electrical characteristic(s) of the drive signal including whether a communication signal is transmitted from another device and generates a digital signal representative thereof.

Abstract: A distributed power management circuit is provided. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.

Abstract: A fast-switching power management circuit is provided. The fast-switching power management circuit is configured to generate an output voltage(s) based on an output voltage target that may change on a per-frame or per-symbol basis. In embodiments disclosed herein, the fast-switching power management circuit can be configured to adapt (increase or decrease) the output voltage(s) within a very short switching interval (e.g., less than one microsecond). As a result, when the fast-switching power management circuit is employed in a wireless communication apparatus to supply the output voltage(s) to a power amplifier circuit(s), the fast-switching power management circuit can quickly adapt the output voltage(s) to help improve operating efficiency and linearity of the power amplifier circuit(s).

Abstract: A feedforward correction block for use in a multi-level output system may include circuitry configured to determine an occurrence of a mode transition between operating modes of the multi-level output system, capture a loop filter output of a signal path of the multi-level output system occurring before and after the occurrence of the mode transition, and based on the transition and a change in the loop filter output responsive to the transition, determine a transition-specific compensation function to apply to a feedforward input signal of the signal path that is combined with the loop filter output.