Abstract: The programmable interconnect points (PIPS) associated with each tile of an FPGA are programmed in response to configuration data values stored in an array of configuration memory cells. Configuration memory cells that control the configuration of the interconnect structure of the tile are located in a rectangular block within the array. For example, the configuration memory cells that control the configuration of the interconnect structure may be located in several rows of the array. This configuration enables the interconnect structure of the tile to be easily modified. To add more interconnect lines to the FPGA, the additional interconnect lines and their associated PIPs are added to the interconnect structure, and the configuration memory cells required to program the PIPs are added as additional rows in the configuration memory cell array. The pattern of configuration memory cells remains unchanged, except for the added rows of configuration memory cells.

Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.