Abstract: Improved redundant relay control circuits are set forth which prevent a load from being energized when any relay coil or contact or stop or start switch contact fails. A first circuit embodiment sets forth a plurality of branches with a cross-monitoring interconnection between a start branch and one of the two other circuit branches. The interconnection prevents a load from being energized when a start switch welds. Second and third circuit embodiments are configured such that the redundant control relay circuit remains inoperative until a fault is cleared although the main power across the circuit is temporarily removed. A fourth circuit embodiment operates independent of relay contact timing.

Abstract: A method of compressing a stream of raw data including the steps of providing a memory device having compression active state and a compression inactive state, inputting a raw data segment into the memory device, generating a compressed data segment based on the raw data segment, creating output data based on the compressed data segment when the memory device is in the compression active state, otherwise based on the raw data segment when in the memory device is the compression inactive state, calculating a compression coefficient, and setting the state of the memory device based on the compression coefficient, such that compressed data is output only when compression has recently proven effective, and raw data is output when compression has recently proven ineffective. The method may also include decompression of the output data.

Abstract: A variable length code decoding circuit provides a positive/negative inversion circuit which directly receives the most significant bit of the shift register receiving the code data. For variable length code data accompanying the sign bit, the positive/negative discriminating processing is performed independently of the decoding processing. Thus, although the size of the variable length code decoding table becomes large and the data length of the codes are increased by one bit, the decoding processing is not dropped because of the increase in the number of the decoding processing cycles. In addition, the variable length code decoding circuit can be used for a color moving image compress technology in accordance with the MPEGI of the ISO standard.

Abstract: A truncation technique for a character code conversion system is disclosed. The truncation technique ensures that a source string received for conversion is accurately converted into a different, target character encoding even when the source string exceeds the length of an input buffer which holds the source string for conversion. The truncation processing technique operates to truncate a portion of the source string held in the input buffer so that the truncated portion is able to be converted to the target character encoding without being affected by subsequent characters in the source string.

Abstract: An electrostatic chuck applicable to, e.g., an epitaxial apparatus or an etching apparatus for electrostatically chucking a semiconductor substrate or wafer is disclosed. The chuck includes a stage for electrostatically retaining the wafer thereon. A plurality of lift pins are elevatable to thrust up the wafer. A plurality of release pins are arranged on the stage for thrusting up the peripheral portion of the wafer. A plurality of drive mechanisms respectively thrust up the release pins stepwise within the allowable elastic deformation range of the wafer. A control device selectively actuates the release pins via the associated drive mechanisms.

Abstract: An analog-to-digital converter includes first current sources, second current sources, current regulators, and conductive channels, with each conductive channel coupled to a respective first current source, second current source, and current regulator. An analog input is split into the first current sources. Each second current source is associated with a unique reference current. At each channel where the first current source couples a larger current than the reference current, the current regulator couples a difference current to allow the second current source to couple the reference current. Alternatively, at each channel where the first current source couples a smaller current than the reference current, the current regulator does not couple a difference current, and the second current source couples the same current as the first current source.

Abstract: An A/D converter and a method of testing the same. Resistors R1 to Rn are connected in series between power-supply terminals receiving a high potential and a low potential, respectively. The potentials at the nodes of the resistors R1 to Rn are input to voltage comparators C1 to Cn-1, respectively. Each comparator compares the input potential with an input signal Vin. The output signals of comparator is supplied to an encoder. The encoder converts the input signals into a digital signal. A test terminal is connected to one of the nodes of the resistors R1 to Rn. Either the high potential at the terminal or the low potential at the terminal is applied to the test terminal to test the A/D converter.

Abstract: A high-order oversampling modulation apparatus is disclosed herein. The present invention implements a high-order oversampling modulation apparatus by use of a plurality of shift registers in response to clock signals provided with a frequency higher than the sampling rate in order to simplify the circuit and layout.

Abstract: A delta sigma modulator includes, an addition circuit with 4 switches, an integration circuit, an analog-digital conversion circuit, a delay circuit, and a digital-analog conversion circuit with 2 capacitors and 6 switches. The addition circuit adds an input signal and a feedback signal, the integration circuit integrates the output of the addition circuit, the analog-digital conversion circuit converts the output of the integration circuit into a digital signal, and the delay circuit delays the output digital signal of the analog-digital conversion circuit.

Abstract: A sensor coil pattern used in combination with a coordinate input apparatus is provided, which is adapted to exactly detecting positions if a noise source such as an converter or an electrically closed conductor exists in the periphery of the apparatus. The apparatus is provided with a sensor surface having a sensor coil pattern of many sensor coils arranged thereon in parallel with each other in position detecting directions, a position indicator, a coil or a resonance circuit incorporated therein and a switching means so connected as to select simultaneously one of a plurality of a sensor coils, wherein said many sensor coils include a predetermined number of sensor coils individually connected to the switching means, said predetermined number of sensor coils including at least one or a plurality of sensor coils counted from one end of the arrangement.

Abstract: An apparatus for encoding a digital signal includes switching means for alternately outputting the digital signal from first and second output terminals at every bit. A first converting means converts the digital signal output from the first output terminal to a signal which will be DC free after NRZI conversion is carried out. A second converting means converts the digital signal output from the second output terminal to a signal which will be DC free. An encoding means is supplied with outputs from the first and second converting means, alternately combining outputs of the first and second converting means at every bit and obtaining a substantially I-NRZI converted digital signal.

Abstract: A solid-state exciter circuit for establishing arc discharges in igniter devices. The exciter circuit includes first and second transformers, first and second main discharge capacitors, and first and second exciter sub-circuits for controlling the charging and discharging of the latter capacitors. The exciter sub-circuits independently generate component ignition or drive pulses each of which has a magnitude and duration that is optimized for a respective part of an ignition event. The exciter circuit then combines these pulses to produce a composite ignition pulse having voltage and current waveforms that so match the discharge characteristics of an igniter that the latter generates an arc of the desired magnitude and duration substantially without being overexcited or underexcited.

Abstract: The present invention relates to variable length coding (VLC). Variable length coding is a widely-used method in data compression, especially, in the applications of video data communication and storage. Many international standards have adopted this technique in video data compression, for example, JPEG, MPEG, CCITT H.261 and so on. Various implementation methods have been proposed for variable length coding. Most of those methods implement the coding with two-field codes. That is, a code is represented by a code word and a code length. However, in this invention, a three-field representation is used for each code. In comparison with the two-field method, this method not only reduces the storage requirements of the code-book but also reduces the hardware or cost to implement a variable length encoder. Moreover, variable length coding can be implemented using both parallel VLC encoders and serial VLC encoders.

Abstract: A self-calibrating high speed D/A converter is provided with a calibration circuit for providing a fixed calibration current and a fixed calibration voltage during calibration mode, and a biasing circuit for biasing the calibration circuit with a first reference voltage and biasing the MSB and LSB array cells with a second reference voltage. By keeping the biasing voltage constant at the array cells during both calibrating and operating modes, such as 12 bits, the D/A converter effectively operates at high resolution, and at high operating speed.

Abstract: RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.

Abstract: A method for compressing a block of input data of predetermined length into a compressed block of output which the use of an expanding input data window. The distance, position and length parameters of each matching string found in the expanding input data window are stored as a combined value which have a one-to-one correspondence to both the distance and length of any given point in the input data block. The combined values can be further encoded by use of a Huffman technique or any other appropriate statistical encoding technique. The combining of a matching string's distance and length parameters into a single value takes advantage of the correlation between the distance and length parameters. This correlation allows the single combined value of distance and length to be more efficiently encoded when using statistical encoding techniques. The technique is especially well adapted to compressing blocks of data of relatively small length.

Abstract: A code table apparatus for a variable length decoder (VLD) is disclosed. The code table apparatus is connected to a barrel shifter to obtain an input code which consists of a code word portion and a sign bit. The code table apparatus comprises a coefficient table for generating a level code and a length code by the code word portion, and a mask circuit for generating a sign bit by a logic operation of the input code and the length code. The coefficient table can decode input codes with opposite sign bits, thus reducing the dimensions of the coefficient table as well as the VLD. Furthermore, since the dimensions of the coefficient table are reduced, the operation time delay of the DCT coefficient table can be shorter, thus improving the performance of the VLD.