Abstract: The present invention relates to a new method for sawing a moulded leadframe package (1) into individual integrated circuits (11). In the present invention sawing of the moulded leadframe package (1) is done on the leads (13) instead of on the connecting bar (14) resulting in less heat being generated during cutting. This results in higher cutting speed and longer dicing blade life.

Abstract: The invention grows SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation is made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. The invention also fabricates silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes can also be performed using microwave power instead of RF power to create plasma.

Abstract: The present invention relates to in-situ techniques for determining process end points in semiconductor wafer polishing processes. Generally, the technique involves utilizing a scanning inspection machine having multiple pair of lasers and sensors located at different angles for detecting signals caused to emanate from an inspected specimen. The detection techniques determine the end points by differentiating between various material properties within a wafer. An accompanying algorithm is used to obtain an end point detection curve that represents a composite representation of the signals obtained from each of the detectors of the inspection machine. This end point detection curve is then used to determine the process end point. Note that computation of the algorithm is performed during the polishing process so that the process end point can be determined without interruptions that diminish process throughputs.

Abstract: An LED array chip comprises a semiconductor substrate having a front surface and a side surface. The first surface and the front surface come together at an end of the chip to define an end portion of said semiconductor substrate that has an acute angle between the first surface and the front surface. The end of the chip defines an outermost dimension of the chip. The first surface extends further away from the front surface than the diffuison depth of the light emitting elements. A method of manufacturing an LED array chip includes the steps of: forming grooves between adjacent LED arrays of the plurality of LED arrays, each of the grooves having opposing side walls each of which makes an acute angle with the front surface; and dicing the semiconductor wafer except for the opposing side walls of each of the grooves to separate the plurality of LED arrays into individual LED array chips.

Abstract: The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

Abstract: A bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a different via density than the other and a method for forming the structure are described. The structure includes a layer of an insulating material such as a low-k dielectric, a first multiplicity of vias formed in a center region of the low-k dielectric material that has a first density, a second multiplicity of vias formed in a peripheral region of the low-k dielectric material surrounding the center region that has a second density, wherein the second density is higher than the first density. A conductive metal pad of generally rectangular shape is then formed on top of and electrically connected to the first and second multiplicity of vias.

Abstract: The present invention is to provide a dicing method of cutting a workpiece along the first streets and the second streets by using a cutting blade having an annular cutting edge provided on the outer peripheral portion on one side surface of a base plate, the workpiece having plural first streets and second streets intersected each other at a predetermined angle. When the second streets are to be cut after the first streets are cut, the cutting blade is so positioned that the side of the base plate faces the side of the unworked region of the workpiece.

Abstract: An integrated circuit device as a first IC chip, a second IC chip, and a circuit board having a hole formed therein that is large enough to permit the second IC chip to be accommodated therein. The first and second IC chips are bonded together so as to be electrically connected together, and the first IC chip is mounted on the circuit board with the second IC chip accommodated in the hole formed in the circuit board. Here, one of the IC chips forming a chip-on-chip structure is accommodated in the hole formed in the circuit board, making further thickness reduction possible. Moreover, the obverse surfaces of the IC chips are located closer to the circuit board, making possible wireless mounting of the IC chips, despite forming a chip-on-chip structure, on the circuit board through connection using bumps. This helps reduce trouble due to inductance in a circuit that handles a high-frequency signal.

Abstract: A method and apparatus for forming a metal-insulator-metal structure on a copper damascene, including a semiconductor device thereof. A copper layer may be initially deposited upon a substrate to form a copper damascene, wherein the copper layer forms a metal layer of a metal-insulator-structure. A barrier layer may then be formed upon the substrate following deposition of the copper layer upon the substrate. Thereafter, the copper layer can be polished utilizing chemical mechanical polishing (CMP) to provide enhanced uniformity of the copper layer, thereby producing a well-controlled metal-insulator-metal structure upon the substrate. The barrier layer formed upon the substrate following deposition of the copper layer may be configured as an in-situ metal barrier. Such an in-situ metal barrier layer may be formed, for example, from tantalum nitride (TaN). The barrier layer may alternatively be configured as a dielectric barrier configured, for example, from NH3 plasma in combination with SiN.

Abstract: The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a photoresist pattern to form a fine line width of about 0.1 &mgr;m or less. A method for forming fine photoresist patterns according to the present invention comprises the step of: forming photoresist patterns over a semiconductor substrate using a stepper; and ashing the photoresist patterns using oxygen radicals in order to decrease line width of the photoresist patterns. The oxygen radicals are formed by a thermal decomposition of an ozone gas in an ozone asher. Accordingly, the present invention overcomes the resolution of the stepper by controlling the ashing rate at a low temperature using the oxygen radicals in the ozone asher.

Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the a second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.

Abstract: A novel copper damascene method for making metal interconnections on semiconductor integrated circuits was achieved. This method avoids overpolishing into a low-k dielectric fluorine-doped glass which would cause copper-flake defects resulting in intralevel electrical shorts. The method utilizes a stacked hard-mask layer on the doped glass layer consisting of a first polish-stop layer, a sacrificial insulating layer and an upper second polish-stop layer. After etching trenches in the stacked hard-mask layer and the doped glass, a copper layer is deposited to fill the trenches and is polished back to the second polish-stop layer. The high polish-back selectivity of the copper to the second polish-stop layer results in improved polish-back uniformity across the substrate. The relatively thin second polish-stop layer can then be polished back and partially into the sacrificial layer without overpolishing and damaging the underlying first polish-stop layer.

Abstract: A method for manufacturing a semiconductor device, comprising controlling a humidity in an atmosphere around a low dielectric constant insulating film at 30% or less, during a processing period and a transfer period between processing equipments, in which at least a part of said low dielectric constant insulating film is exposed to the atmosphere.

Abstract: A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.

Abstract: A method of manufacturing a contact plug in a semiconductor device is disclosed. In-situ thermal doping of an impurity such as phosphorous (P) during the process by which polysilicon for a contact plug is formed by selective growth method and after in-situ doping after the growth process is employed in order to increase the concentration of the impurity in the contact plug. As a result, the disclosed method can reduce the interfacial resistance at the plug to improve the electrical characteristics of a device of more than 1 G bits.

Abstract: A semiconductor wafer manufacturing process is disclosed wherein extremely flat, double side polished semiconductor wafers having enhanced gettering characteristics on the back surface are produced. The process includes creating an enhanced gettering layer on the back surface of a double side polished semiconductor wafer. A protective layer is subsequently grown on the enhanced gettering layer and the wafer is subsequently subjected to a second double side polishing operation. Finally, the protective layer is removed and the front surface final polished to produce an extremely flat semiconductor wafer having enhanced gettering characteristics on the back surface.

Abstract: The invention provides a method for depositing a film on a surface of a semiconductor wafer while preventing formation of defects on the surface of the wafer. The method includes selecting a quartz wafer carrier for holding the semiconductor wafer during the depositing of the film, where the wafer carrier has quartz rods with fire-polished slots for receiving an edge of the semiconductor wafer. The semiconductor wafer is placed into the quartz wafer carrier with the edge of the wafer disposed within the fire-polished slots, and the wafer carrier and wafer are loaded into a deposition chamber. Air is evacuated from the deposition chamber, the temperature in the chamber is raised to a deposition temperature, the pressure within the deposition chamber is adjusted to a deposition pressure, and process gases are introduced to the deposition chamber. By reaction of the process gases, the film is deposited on the surface of the wafer and on the wafer carrier.