Patents Examined by Toan Tran
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Patent number: 6504405Abstract: A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.Type: GrantFiled: December 6, 2001Date of Patent: January 7, 2003Assignee: Rambus Inc.Inventors: Huy M. Nguyen, Benedict C. Lau
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Patent number: 6504404Abstract: A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.Type: GrantFiled: January 3, 2002Date of Patent: January 7, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Uchiki, Harufusa Kondoh
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Patent number: 6498517Abstract: Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.Type: GrantFiled: November 28, 2001Date of Patent: December 24, 2002Assignee: Canon Kabushiki KaishaInventor: Keizo Miyazaki
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Patent number: 6496050Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.Type: GrantFiled: June 21, 2001Date of Patent: December 17, 2002Assignee: STMicroelectronics LimitedInventor: Alan Lloyd
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Patent number: 6492845Abstract: A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.Type: GrantFiled: December 27, 2001Date of Patent: December 10, 2002Assignee: Shenzhen STS Microelectronics Co. Ltd.Inventors: Weiguo Ge, Congqing Xiong
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Patent number: 6489817Abstract: A clock divider is described.Type: GrantFiled: September 26, 2001Date of Patent: December 3, 2002Assignee: Altera CorporationInventors: Choong Kit Wong, Sammy Cheung, Boon Jin Ang
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Patent number: 6489813Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.Type: GrantFiled: February 26, 2001Date of Patent: December 3, 2002Assignee: Texas Instruments IncorporatedInventors: Suhas R. Kulhalli, Ravishankar S. Ayyagari
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Patent number: 6486725Abstract: A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysterisis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system.Type: GrantFiled: December 8, 2000Date of Patent: November 26, 2002Assignee: Siemens Energy & AutomationInventors: Mark Steven Boggs, Temple L. Fulton, Steve Hausman, Gary McNabb, Alan McNutt, Steven W. Stimmel
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Patent number: 6483352Abstract: A current mirror sense amplifier, with a two-stage current mirror, a first transistor, and a second transistor. The first transistor and the second transistor each have first and second connection terminals. The current mirror has a current input terminal and a current output terminal. The first transistor has a gate electrically connected to a pre-charge voltage. The first connection terminal of the first transistor is electrically connected to a reference voltage. The second transistor has a gate electrically connected to a reference signal. The first connection terminal of the second transistor is electrically connected to the reference voltage. The second connection terminals are connected to the current output terminal in parallel.Type: GrantFiled: January 14, 2002Date of Patent: November 19, 2002Assignee: Macronix International Co., Ltd.Inventors: Sheng-Chang Kuo, Ti-Wen Chen
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Patent number: 6483351Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.Type: GrantFiled: November 26, 2001Date of Patent: November 19, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Yoon Sim
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Patent number: 6483359Abstract: A delay locked loop (DLL) is disclosed which has finer adjustability.Type: GrantFiled: June 29, 2001Date of Patent: November 19, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Seong-Hoon Lee
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Patent number: 6480038Abstract: A bipolar comparator with an asymmetric differential amplifier stage is described. The comparator has two transistors, and the control electrodes of which are short circuited to one another. The two transistors have load paths that are connected in series in each case with one current source between one input terminal and a supply terminal. An output terminal is connected to the second current source and to a load electrode of the second transistor, at which output terminal an output signal can be picked up. A third transistor is provided with a load path disposed in parallel with the load path of the first transistor. The first current source generates a first operating current being a multiple of the second operating current generated by the second current source and the multiple corresponds to an effective area ratio of the first and third transistor with respect to the second transistor.Type: GrantFiled: October 29, 2001Date of Patent: November 12, 2002Assignee: Infineon Technologies AGInventor: Wolfgang Horn
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Patent number: 6480037Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.Type: GrantFiled: November 27, 2001Date of Patent: November 12, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joong Song, Jin-Uok Lee
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Patent number: 6480044Abstract: A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.Type: GrantFiled: March 12, 2001Date of Patent: November 12, 2002Assignee: Infineon Technologies AGInventors: Georg Braun, Heinz Hönigschmid, Kurt Hoffmann, Oskar Kowarik
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Patent number: 6476659Abstract: A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.Type: GrantFiled: November 21, 2001Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Vimal Ramannhai Patel, Curtis Walter Preuss, Daniel Guy Young
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Patent number: 6476648Abstract: An improved sample and hold circuit for analog-to-digital conversion. The improvement incorporates an asymmetric drive high gain operational amplifier to rapidly slew the input voltage for maintaining a high sample rate. The asymmetric drive high gain operational amplifier allows increased current to be delivered in a uni-directional manner. The input nodes of the high gain operational amplifier are pre-charged to a predetermined reference voltage which further enhances the acquisition time. The asymmetric drive high gain amplifier may be switched off to conserve power consumption.Type: GrantFiled: March 18, 2002Date of Patent: November 5, 2002Assignee: Microchip Technology IncorporatedInventor: Michael J. Brunolli
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Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit
Patent number: 6476645Abstract: A method and apparatus for mitigating the history effect in silicon-on-insulator (SOI)-based circuitry, e.g., data interface circuitry operable as a single-ended off-chip signal receiver in a VLSI component such as a microprocessor. A sense amplifier (sense amp) latch circuit arrangement includes a sense amp operable to sense data and a latch operable to hold the sensed data. When data is available, the sense amp generates a pair of complementary data signals responsive to a control signal used for alternating the sense amp's operation between an evaluation phase and an equilibration (i.e., pre-charge) phase. A feedback circuit portion is operable to modify the control signal's logic state within a clock phase associated with one of the two complementary clocks provided to the interface circuitry. Since the equilibration phase is entered combinationally off the evaluation phase, both evaluation and equilibration can be triggered from the same clock edge.Type: GrantFiled: August 10, 2001Date of Patent: November 5, 2002Assignee: Hewlett-Packard CompanyInventor: Philip L. Barnes -
Patent number: 6476647Abstract: A method and circuit arrangement for processing analog signals in applications in which low energy consumption is of the essence. An integrator topology where the active charge-transferring element is preferably a source-follower-type transistor in which one input terminal is arranged so as to be substantially independent of the input signal and in which the essential signal path elements of the circuit topology are connected in a fixed manner. Preferably, the circuit arrangement is realized so that it comprises separate transistors for sampling and charge transfer. Thus it is possible to connect an input signal in a fixed manner in an input terminal of the sampling transistor, and an input terminal of the charge-transferring transistor can be connected in a fixed manner to a constant voltage. By using a signal processing circuit according to the invention, it is possible to avoid circuit non-idealities caused by parasitic capacitances.Type: GrantFiled: January 4, 2001Date of Patent: November 5, 2002Assignee: Nokia Mobile Phones Ltd.Inventor: Harri Rapakko
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Patent number: 6472913Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.Type: GrantFiled: January 26, 2001Date of Patent: October 29, 2002Assignee: Oki Electric Industry Co., LtdInventor: Kenichi Natsume
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Patent number: 6472931Abstract: One embodiment of the present invention provides a system for amplifying an input signal received from a capacitive sensor. The system includes an input for receiving an input signal from the capacitive sensor and an amplifier that amplifies the input signal to produce an output signal. This amplifier includes a pull-up circuit that pulls the output signal up to a high voltage when the input signal exceeds a threshold voltage. It also includes a pull-down circuit that pulls the output signal down to a low voltage when the input signal falls below the threshold voltage. After the output signal is pulled up to the high voltage, the pull-up circuit enters a refractory state in which the pull-up circuit uses a limited current, and the pull-down circuit enters a receptive state in which the pull-down circuit is sensitized to react to small changes in the input signal.Type: GrantFiled: November 16, 2001Date of Patent: October 29, 2002Assignee: Sun Microsystems, Inc.Inventors: Robert J. Drost, Sharon Sookdeo-Drost