Patents Examined by Tom Stevens
  • Patent number: 7216066
    Abstract: A method is presented comprising assigning each of a plurality of segments comprising a received corpus to a node in a data structure denoting dependencies between nodes, and calculating a transitional probability between each of the nodes in the data structure.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: May 8, 2007
    Assignee: Microsoft Corporation
    Inventors: Shuo Di, Kai-Fu Lee, Lee-Feng Chien, Zheng Chen, Jianfeng Gao
  • Patent number: 7200539
    Abstract: A method for predicting the on-set of sand production or critical drawdown pressure (CDP) in high flow rate gas wells. The method describes the perforation and open-hole cavity stability incorporating both rock and fluid mechanics fundamentals. The pore pressure gradient is calculated using the non-Darcy gas flow equation and coupled with the stress-state for a perfectly Mohr-Coulomb material. Sand production is assumed to initiate when the drawdown pressure condition induces tensile stresses across the cavity face. Both spherical and cylindrical models are presented. The spherical model is suitable for cased and perforated applications while the cylindrical model is used for a horizontal open-hole completion.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: April 3, 2007
    Assignee: Baker Hughes Incorporated
    Inventors: See Hong Ong, Gangerico G. Ramos, Ziqiong Zheng
  • Patent number: 7200544
    Abstract: There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit description and ones of the plurality of HDL modules, the circuit netlist is responsible for defining behavioral relationships among associated ones of the HDL modules, and associate a timing-violation controller with the circuit netlist to ignore selected timing violations sensed as a function of various ones of the behavioral relationships during simulation of the desired circuit.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: April 3, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Hal C. McCown
  • Patent number: 7197437
    Abstract: A Monte Carlo ion implantation simulation method includes finding a unit cell in which an implanted trial particle is present, finding a basic cell in which the trial particle is present among basic cells that form the unit cell, finding a directional range in which the trial particle travels, obtaining collision candidate atoms with their locations from a database according to the found basic cell and directional range, setting a thermal vibration displacement for each of the collision candidate atoms that has not set thermal vibration displacement, calculating a collision parameter and free-flight distance for each of the collision candidate atoms, selecting, as a collision atom, one of the collision candidate atoms that has a collision parameter smaller than a predetermined maximum collision parameter and a smallest positive free-flight distance, and calculating a collision between the trial particle and the collision atom to find the after-collision location and momentum of the trial particle.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takahisa Kanemura
  • Patent number: 7191112
    Abstract: Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: March 13, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael J. Demler, Stephen Lim, Geoffrey Ellis
  • Patent number: 7149663
    Abstract: A method for selecting an order in which to sift variables in a binary decision diagram. The method includes an act of arranging the variables of the binary decision diagram on nodes of a graph, with the nodes of the graph being labeled with the variables of the system such that a set of functions labeling the leaves reachable from a node correspond to the set of functions which depend on the variables labeling the node. The method further includes an act of traversing the graph in a depth first manner to produce a list of the labels in the selected order.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: December 12, 2006
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: Geoff Barrett
  • Patent number: 7133819
    Abstract: Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: November 7, 2006
    Assignee: Altera Corporation
    Inventor: Michael D. Hutton
  • Patent number: 7130783
    Abstract: System, methods, and apparatus for verifying microcircuit designs by interleaving between random and formal simulation techniques to identify input traces useful for driving designs under test into sequences of device states. In a method aspect the invention provides process for beginning random simulation of a sequence of states of a microcircuit design by inputting a sequence of random input vectors to a design under test model in order to obtain a sequence of random simulation states; monitoring a simulation coverage progress metric to determine a preference for switching from random simulation to formal methods of simulating states in the design under test; beginning formal simulation of states in the design under test and monitoring a formal coverage progress metric to determine a preference for resuming random simulation of states of said microcircuit design; and resuming random simulation.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: October 31, 2006
    Assignee: Synopsys, Inc.
    Inventors: Kevin M. Harer, Pei-Hsin Ho, Robert F Damiano
  • Patent number: 7120570
    Abstract: A design tool for choosing and modifying features of a dot matrix display. The design tool allows a user to design and save a character set and then to enter and view text to be displayed using the character set. The user is able to modify features of the display and to immediately see the result of any modifications made. The user may further see a representation of a hardware display having features and characteristics selected by the user, and may modify the features as desired. As the modifications are made, they are reflected in the representation of the hardware display. The design tool allows the user to store numerical representations of the selected features and characteristics of the design in order to provide the numerical representations to personnel implementing a hardware embodiment of the design.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: October 10, 2006
    Assignee: NCR Corporation
    Inventor: William Douglas Poynter
  • Patent number: 7120568
    Abstract: A method for verification includes providing an implementation model, which defines model states of a target system and model transitions between the model states, and providing a specification of the target system, including properties that the system is expected to obey. A tableau is created from the specification, the tableau defining tableau states with tableau transitions between the tableau states in accordance with the properties. The tableau transitions are compared to the model transitions to determine whether a discrepancy exists therebetween.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: October 10, 2006
    Assignee: Marvell Semiconductor Israel Ltd.
    Inventors: Daniel Geist, Orna Grumberg, Sagi Katz
  • Patent number: 7117136
    Abstract: An input and feedback system for use with simulator devices immobilizes a portion of the user's body using a securement device which holds the immobilized portion in a fixed position. Pressure sensors are disposed upon the securement device to detect the force resulting from any attempted motion of the immobilized body part. Signals describing these forces are sent to a processing unit which applies this information to a simulated environment and provides sensory feedback to the user of the this simulated environment. Feedback is provided via vibrating elements which provide a sensation to the user corresponding to the motion of the user's muscles which occur in the simulated environment. Feedback is also provided via a screen which is disposed in front of the head of the user. Such immobilizing devices may be used to allow input and feedback based on the motion of various parts of the user's body, such as the head, arms, legs, and torso.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: October 3, 2006
    Assignee: Linden Research, Inc.
    Inventor: Philip Rosedale
  • Patent number: 7110927
    Abstract: A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler has a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: September 19, 2006
    Assignee: Altera Corporation
    Inventors: Tony San, Philippe Molson
  • Patent number: 7107203
    Abstract: A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: September 12, 2006
    Assignee: Quickturn Design Systems Inc.
    Inventors: William F. Beausoleil, R. Bryan Cook, Tak-kwong Ng, Helmut Roth, Peter Tannenbaum, Lawrence A. Thomas, Norton J. Tomassetti
  • Patent number: 7103520
    Abstract: A modeling system predicts natural frequency responses in tube sub-systems including shrouded bellows components. The system determines a stiffness multiplier from input values and uses the determined flexibility factor to determine the natural frequency responses. The input values include geometry inputs and dynamic operating condition inputs. The flexibility factor is determined with a regression equation. The regression equation, based on dynamic stiffness test data of various shrouded bellows configurations, permits the system to characterize the shrouded bellows using a geometry element that includes an assigned flexibility factor based on dynamic stiffness test data.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 5, 2006
    Assignee: General Electric Company
    Inventors: Mark Richard Shaw, Christen Staton Vonderau
  • Patent number: 7103525
    Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Makoto Suwada, Tatsuo Koizumi, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda
  • Patent number: 7103524
    Abstract: A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Then, for each of the smaller simpler extraction problems, complex mathematical models are created using machine learning techniques.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 5, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 7103516
    Abstract: A model optimization apparatus detects redundant shapes, such as two shapes offsetting each other, pattern shapes, etc. in editing data of a plurality of shapes forming a three-dimensional model, deletes the data of the redundant shapes, and releases and reconstructs the relationship between shapes, thereby optimizing the data structure.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventor: Masahira Deguchi
  • Patent number: 7103526
    Abstract: A method for exposing the internal signals of a system model or software model of a dynamic system to a client application outside the original modeling environment is provided. A designer of the system model is provided with a way to select internal signals of the system model in order to expose those internal signals to other computer applications external to the modeling environment. Such computer applications are then able to access the internal signals by way of interfacing software while the system model is being exercised within the modeling environment, or while a software model based on the system model is executed outside of that environment.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: September 5, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Richard Craig Allen, Randy A Coverstone
  • Patent number: 7099808
    Abstract: A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for timing and noise circuit simulations, particularly for deep sub-micron circuit design simulations. Briefly, a measurement of both total capacitance of a line and cross coupling capacitance between two lines is determined by applying predetermined voltage signals to specific circuit elements. The resulting current allows simple computation of total capacitance and cross coupling capacitance. Multiple cross coupling capacitance can be measured with a single device, thus improving the art of library generation, and the overall method is free of uncertainties related to transistor capacitance couplings.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: August 29, 2006
    Assignee: Mentor Graphics Corp.
    Inventors: Roberto Suaya, Sophie H. M. Billy
  • Patent number: 7099812
    Abstract: The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarations 72 that each correspond to a functional attribute and list at least two valid functional states, logic expressions 78 that test for the functional states and set axis variables, and a grid declaration 80 that converts the axis variables to a unique linear index value corresponding to the cross-product of the achieved functional states and records hits. The linear index is calculated by multiplying the integer value of each axis variable (except the nth axis variable) by the product of the sizes of each higher-order axis than the axis to which said axis variable corresponds, summing the results, and adding the integer value of the nth said axis variable.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 29, 2006
    Assignee: Intrinsity, Inc.
    Inventor: Fritz A. Boehm