Abstract: A method and apparatus for performing signal interval timing analyses using a multi-channel logic analyzer and a host computer. Timing signal intervals to be measured are defined by an operator in a standard format. Timing signal interval data and sampling methodology is transmitted from the host computer to the logic analyzer. The logic analyzer captures and records the signal interval samples and transmits the samples to the host computer. The host computer translates the samples into a device neutral format, measures the time intervals for the samples and performs a statistical analysis on the measured intervals. The results of the statistical analysis, including range, distribution and mean values for the samples is graphically displayed.

Abstract: A method and apparatus are disclosed for the efficient generation of cyclic redundancy check (CRC) codes employing CRC generator polynomials of the form (1+x).multidot.f(x). The efficiency is achieved by independently and concurrently generating in parallel a preliminary CRC code word corresponding to f(x) and a term corresponding to (1+x) over a message M(x). The term corresponding to (1+x) is generated in a manner to have either a zero (0) state or a one (1) state. Then, the term corresponding to (1+x) is used to modify the preliminary CRC code word to obtain an overall CRC code word being generated over message M(x). If the term corresponding to (1+x) is a 0 state, then the overall CRC code word is obtained by shifting the bits of the preliminary CRC code word once to the left. If the term corresponding to (1+x) is a 1 state, then the overall CRC code word is obtained by shifting the bits of the preliminary CRC code word once to the left and adding f(x) to the shifted preliminary CRC code word.

Abstract: Method for reducing bit errors in digital communication systems. Bit falsifications can occur in the throughconnection of bit streams composed of a plurality of information words in the switching networks of digital communication systems. Correcting these bit errors presents problems in practice. Given redundantly executed, respectively activated switching network halves, only the correctly through-connected information word is forwarded to the terminal subscriber after the through-connection. Whether an information word was correctly through-connected is identified after the through-connection with a combined parity bit check and a bit-by-bit comparison of information words that are through-connected in parallel.

Abstract: On-the-fly error correction is provided using syndromes of a codeword encoded on data storage media. First and second syndromes are generated and a variable prescaler prescales the second syndrome by a field element to produce a prescaled second syndrome where the field element is variable. The error value is determined based on the first syndrome, and the error location is determined based on a comparison between the error value and the value of the prescaled second syndrome. The error value located at the error location is then corrected.

Abstract: A memory fault mapping apparatus detects faults generated in a memory array during on-line operation. As the memory array is randomly accessed, single bit error are detected, corrected, and mapped into an error memory. The errors may be mapped in an error memory having a memory location for each memory of the memory array or alternatively, by grouping memories together and when the errors generated by any one group exceeds a predetermined threshold of errors, testing only the memories in that group off-line. By grouping the memories a substantial reduction in the amount of error memory required can be achieved. A SEC/DED syndrome generator detects single and double bit errors, correcting the single bit errors while providing an indication of which memory generated the error. An error memory stores error counts for the memory array, each error count indicating the number of errors for a specific memory or a group of memories.

Abstract: There is provided a test method for a semiconductor memory device which can be applied to a margin test, for example. The memory device has two types of sense amplifiers each composed of a layout pattern symmetrical to the other and arrayed such that the layout patterns alternate, memory cells, bit lines which are connected to the sense amplifiers and which carry signals expressing data stored in the memory cells, work lines, gates connected to bit lines, and a comparator which receives signals on bit lines via the gates and determines whether or not the signals match.

Abstract: In a memory tester for testing memories of the type having a polarity inversion feature there are provided a bit select circuit for selecting from an address generated by an address generator a plurality of bits necessary for a logical expression expressing a polarity-inverted data storage area of the memory under test and a bit register circuit for storing bit data which is used to supply the bit select circuit with a select signal for specifying bits to be selectively output. The bits selectively output by the bit select circuit are used as an address for reading out a polarity inversion control signal from an area inversion memory. A polarity inverter, supplied with test data signal from a data generator, outputs the test data intact or after inverting its polarity in accordance with the logic of the polarity inversion control signal, and the output data is written into the memory under test.