Abstract: A circuit for supplying a periodic, essentially parabolic signal by squaring a sawtooth-shaped signal. For eliminating a disturbance occurring during the retrace period, a signal is generated during this period whose polarity is opposite to that of the parabolic signal occurring during the trace period, both the generated signal and the derivative with respect to time of this signal assuming values at the start and end of the retrace period which are substantially equal to the corresponding values at the same instants of the essentially parabolic signal occurring during the trace period, and of the derivative with respect to time of this signal.

Abstract: A liquid crystal antidazzle mirror comprising discharging electrodes respectively provided at electrodes of liquid crystal electrodes, a grounding electrode opposed to the discharging electrodes for discharging a static electricity charged in the liquid crystal section between the discharging electrodes and the grounding electrode. Thus, the antidazzle mirror can protect itself against a static electricity.

Abstract: A pin hole camera assembly for use in viewing an object having a relatively large light intensity range, for example a crucible containing molten uranium in an atomic vapor laser isotope separator (AVLIS) system is disclosed herein. The assembly includes means for optically compressing the light intensity range appearing at its input sufficient to make it receivable and decipherable by a standard video camera. A number of different means for compressing the intensity range are disclosed. These include the use of photogray glass, the use of a pair of interference filters, and the utilization of a new liquid crystal notch filter in combination with an interference filter.

Abstract: A first node is connected to an external power source via a switch. A second node is connected to an internal power source whose voltage is lower than that of the external power source. The first and second nodes are connected to an output node via first and second MOSFET switches. The output node is connected to a semiconductor circuit. The potentials at the first and second nodes are compared with each other by a voltage comparator connected between the output node and ground. A MOSFET is quickly turned on and off in response to the potential at the first node.

Abstract: This circuit comprises a current source stage connectable to a capacitor which is controlled so as to alternately and periodically charge with the current fed by the source stage and discharge through a switch element, so as to generate a saw-tooth wave voltage. A buffer circuit, with low-impedance output is connected to the capacitor, for feeding a saw-tooth shaped low-impedance voltage signal to a load. In order to prevent the bias current of the buffer stage from introducing an error in the capacitor charge current and in the frequency of the saw-tooth voltage, a current sensor is provided connected between the buffer stage and the current source stage so as to vary the current generated by the source stage in an equal but opposite manner with respect to the error current due to the buffer stage.

Abstract: A liquid crystal antidazzle mirror for turning OFF a power of a liquid crystal drive control circuit by a power switch provided between the liquid crystal drive control circuit and a power source comprising a capacitor of a predetermined capacity disposed between the power switch and the liquid crystal drive control circuit and connected in parallel between power lines to supply power from the capacitor to at least a mode memory circuit in the liquid crystal drive control circuit for a predetermined time determined by the discharging characteristic of the capacitor when the power switch is opened. Thus, the mirror can reset the set mode of the antidazzle mirror to the used mode immediately before a power switch is opened when the power switch is closed within a predetermined time after the power switch is opened.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: A sense circuit of a semiconductor memory transistor includes a bit line connected to a memory cell which stores "1" or "0". The sense circuit includes a MOS transistor which has its gate connected to the bit line, its source connected to ground voltage and its drain connected to a supply voltage through a load MOS transistor. The sense circuit also includes a compensating circuit for compensating the voltage at the bit line when the ground voltage has fluctuated. For example, the compensating circuit includes a pull-up circuit for pulling up the voltage at the bit line when the ground voltage has shifted to the positive side and a pull-down circuit for pulling down the voltage at the bit line when the ground voltage has shifted to the negative side, thereby maintaining the relative voltage relationship between the voltage at the bit line and the ground voltage at a proper value.

Abstract: An electronically variable active analog delay line utilizes cascaded differential transconductance amplifiers with integrating capacitors and negative feedback from the output to the input of each noninverting amplifier. The delay of each section may be controlled through a conductor having distributed resistance connected at distributed points to the transconductance control terminal of the amplifiers with a controllable voltage gradient between the two ends of the conductor. Signals may be coupled in and added to a propagating signal using capacitors, or transconductance amplifiers which may also be of the differential transconductance type, particularly when coupling signals from a second delay line having substantially the same propagation velocity.

Abstract: A liquid crystal cell comprises a liquid crystal sealed between a pair of confronting transparent substrates. A multiplicity of semiconductor driver elements are substantially uniformly distributed over an inner surface of one of the substrates. The semiconductor driver elements have output electrodes connected respectively to matrix element electrodes formed on the inner surface of said one of the substrates. A driver circuit is formed as a semiconductor integrated circuit on an extension of the inner surface of said one of the substrates for selectively driving the semiconductor driver elements.

Abstract: An automatic liquid crystal light-shutter which detects directly the flashing light generated by an alternating current electric welding machine, by means of a photo diode detector and then converts the detected light into an alternating signal current. Then this signal current is filtered to remove miscellaneous signals, amplified and rectified. Next, the rectified signal is fed to an inverter circuit which controls the oscillating of an oscillating circuit that operates a liquid crystal display to function very swiftly.

Abstract: A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a "H" level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the "H" level or the "L" level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.

Abstract: In a voltage-switching device for such applications as the control of electron tube grids in the field of radar or telecommunications, the total voltages to be switched are distributed at the terminals of a series-connected array of MOS field-effect transistors, thereby ensuring that each individual transistor is not liable to carry voltages in excess of such values which could result in transistor damage or destruction.

Abstract: A multiplexed driving method of an optical switching element employing ferroelectric liquid crystal with a negative dielectric anisotropy including signal electrodes and common signal electrodes arranged in matrix and a ferroelectric liquid crystal layer disposed therebetween so as to constitute pixels at the respective facing portions of the signal electrodes and the common signal electrodes comprising a step of applying a common writing signal voltage to one of the common signal electrode to select pixels to which information be written, simultaneously applying a common status holding AC signal voltage to the other common signal electrodes covering non-selected pixels and simultaneously applying one of two signal pulses with opposite polarities to the signal electrodes, whereby resultant information writing voltages formed in combination of the common writing signal voltage and the signal pulses, which are enough to determine the orientation of the ferroelectric liquid crystal molecules, are applied on the

Abstract: A main potential generating circuit 11a receives AC voltage from a first AC power supply 40 and charges a substrate potential output terminal 9 with a prescribed potential. On the other hand, a reference potential generating circuit 11b receives AC voltage from a pulse generating circuit 3 as a second AC power supply and charges a reference potential point 9b with a prescribed potential. A differential amplifying circuit 20 detects difference between the potential of the substrate potential output terminal 9 and the potential of the reference potential point 9b and only when the difference is detected, it operates the first AC power supply 40 to charge the substrate potential output terminal 9.

Abstract: An impulse generator for detecting an edge of an input pulse. The impulse generator comprises a first and second transistors connected to turn on at the occurrence of a signal pulse on an input line, with the second transistor connected to operate in its inverse mode so that it has a longer turn-on time. The second transistor is connected in such a manner as to draw current away from the base of the first transistor when the second transistor turns on, thereby causing an impulse to be generated at the output terminal of the first transistor, regardless of the width of the input pulse.

Abstract: A limiter for limiting an input signal includes a first clamping circuit for clamping the input signal at a first level so that the input signal cannot rise substantially above such first level, a second clamping circuit for clamping the input signal at a second level less than the first level so that the input signal cannot drop substantially below such second level and a single operational amplifier having an input which receives the clamped input signal and an output at which is developed an output signal that is a scaled version of the clamped input signal. The limiter may be used as either a static or dynamic limiter, is simple in design, inexpensive, and can be used in a wide variety of applications.

Abstract: The present invention relates to a conversion circuit having a differential input in CMOS logic levels, this circuit comprising an input comparator comprising two NPN type bipolar transistors, connected by their emitters and receiving differential input signals on their bases; a CMOS flip-flop comprising two branches each constituted by a P-channel MOS transistor in series, with two N-channel MOS transistors of each branch being connected in order to set the current of these branches at the passing state, the gates of the first N-channel MOS transistors of each branch being connected to the drains of the P-channel transistors of the other branch and to an output terminal. This circuit can be used in plasma panel command operations.

Abstract: For improvement in switching speed, there is provided a Schmit trigger circuit comprising a high-voltage supply line, a low-voltage supply line, a series combination of a bipolar transistor and a resistor provided between the high-voltage supply line and the low-voltage supply line, the bipolar transistor having a base node connected to an input terminal, an intermediate node provided between the bipolar transistor and the resistor, a logic gate having an output node and two input nodes connected to the input terminal and the intermediate node, respectively, and a field effect transistor operative to establish or block a current path between the intermediate node and one of the high-voltage supply line and the low-voltage supply line, the field effect transistor having a gate node connected to the output node of the logic gate.

Abstract: A technique for subtracting images in real time utilizing a single liquid crystal light valve (LCLV) is described. The two images are projected on the LCLV through a common grating in a well-determined geometry. The interrogating light beam is optically filtered, so that only different features in the two images are revealed.