Abstract: A telemetry receiver which is capable of automatically recognizing certain incompatible code formats and correctly decoding received data from a remotely located telemetry transmitter is disclosed. The specific embodiment is an end of train receiver mounted in the cab of a locomotive which receives encoded transmissions, including encoded brake pipe pressure data, a transmitter mounted on the last car of a train. The receiver permits telemetry equipment to be "mixed-and-matched"; that is, the receiver in the locomotive will respond to the transmissions of a telemetry transmitter attached to the last car of the train no matter what the vendor source. The telemetry receiver is provided with a microprocessor which analyzes the received transmission. The microprocessor is programmed to recognize certain known transmission protocols and formats and then invoke the correct routine for decoding the received data.

Abstract: At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronzied with each other except during the power up phase. The DASD synchronization is controlled and maintained by synchronization control means independent of any commands from the CPU. When one or more commands such as SEEK and SET SECTOR or LOCATE commands are transferred from the CPU to a control unit over a single data transfer path between them, desired identical records on the synchronized DASDs are concurrently located while the DASDs are disconnected from the data transfer path. Upon locating the desired identical records, the DASDs are reconnected to the data transfer path. Then, a WRITE command is transferred from the CPU to the control unit for concurrently recording the same data onto the synchronized DASDs at the desired record locations.

Abstract: A digital logic circuit is broken into functional blocks, each having a path from its output port to a chip level output port. No two input patterns to that path produce the same output pattern on that path and for every path input pattern there is a one-to-one relation with the path output pattern regardless of the transformation of that pattern by the path. All other path inputs are independent of the path test patterns such that a block test output pattern applied to that path is not fault affected by those other path inputs. The circuit is partitioned into testable blocks whose outputs are coupled by such paths to observable chip output ports. The chip level tests for all block test patterns are screened to eliminate redundant block tests to produce a practical set of test vectors.

Abstract: An oil change interval monitor is provided which senses diesel engine variables such as oil temperature, fuel flow and the volume of oil added to the engine since the last oil change and combines these variables with values determined by known engine parameters to provide a continuously updated indication of the percentage of oil life used by the engine since the last oil change.

Abstract: An interactive method for testing vehicle electronics systems is disclosed in which various vehicle subsystems are exercised under the control of the tester unit while the performance of associated subsystems are monitored to detect and isolate malfunctions. The tester includes interchangeable program cartridges that can be easily inserted to adapt the unit for a variety of different vehicles and test procedures, and also optional interchangeable input/output cartridges for test procedures in which additional access to or from the tester or peripheral devices is necessary. The test unit accesses the vehicle's electronics data bus by means of an assembly line diagnostic link, the access being accomplished via a multiplexer that makes it possible to locate faults on the data bus itself. The tester greatly reduces the time and effort necessary to analyze malfunctions in the field, and is considerably more comprehensive than prior test equipment.

Abstract: A device for synchronizing the output test pattern signals of a test circuit with the clock signal of a device under test (DUT). The invention uses a programmable delay in the feedback loop of a phase locked loop system to adjust the phase of the test pattern signals to be synchronized with the clock of the device under test (DUT).

Abstract: A method for the determination and display of signal arrival time, intensity, and direction for use with time domain measurements. The method may be implemented by either hardware or by software and includes obtaining at least four separate time domain measurement, such as energy time curves (ETCs), at ninety degree intervals on a horizontal plane. Opposing ETCs are differenced to obtain X and Y Cartesian components. For display in a polar format to illustrate the direction of arrival the X and Y components are converted into an angular value. The angular value determining the theta angle and either the time of arrival or intensity expressed in X and Y components establish the polar vector length. To display a three dimensional space two more ETCs are obtained in a vertical plane and correlated in the manner described above.