Patents Examined by Tuan Dinh
  • Patent number: 7259336
    Abstract: A technique for improving power/ground flooding is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving power and ground flooding in a multilayer circuit board, the multilayer circuit board having a plurality of signal layers. The method may comprise forming a plurality of electrically conductive vias, wherein each of the plurality of electrically conductive vias extends through one or more of the plurality of signal layers. The method may also comprise routing signals associated with the plurality of electrically conductive vias, thereby creating at least one power/ground flooding channel. The method may additionally comprise forming at least one power/ground connection within the at least one power/ground flooding channel.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: August 21, 2007
    Assignee: Nortel Networks Limited
    Inventors: Aneta Wyrzykowska, Herman Kwong, Luigi Difilippo
  • Patent number: 7259967
    Abstract: A Universal-Serial-Bus (USB) device includes a PCBA mounted inside a molded plastic housing structure such that metal contacts are exposed on a plug portion of the housing structure, and includes a plastic plug shell integrally molded to the housing structure such that an upper wall of the plug shell is spaced from the metal contacts by a predetermined gap distance. A USB controller IC is mounted onto a relatively narrow portion of the PCBA under the metal contacts to reduce overall length of the USB device. An optional locking collar strengthens a rear edge of the plastic plug shell and front handle wall of the housing structure. An optional rear cover is attached over a rear opening of the housing structure and secures a rear edge of the PCBA.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Super Talent Electronics, Inc.
    Inventor: Jim Ni
  • Patent number: 7256995
    Abstract: An electronics module comprises a housing; and a plurality of electronic and electrical components for example fans. The module includes electromagnetic shielding for example perforated panels side walls etc. that is associated with the housing and/or the electronic components, and which provides a Faraday cage for the electronic components. The shielding is constructed so that one or more of the components can be removed from the module while the module is in operation substantially without affecting the integrity of the Faraday cage. The module enables certain components thereof to be replaced without adding to the downtime of the system or increasing electromagnetic interference.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: August 14, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Sean Conor Wrycraft, Brian Benstead
  • Patent number: 7257005
    Abstract: A portable device includes a first casing which houses a circuit board having a first conductive layer, a second casing which houses a circuit board having a second conductive layer, and a coupling part which openably and closably couples the first casing and the second casing. The coupling part is made of a metal material, and the first conductive layer is electrically connected to the second conductive layer via the coupling part.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 14, 2007
    Assignee: Kyocera Corporation
    Inventor: Kazuki Kato
  • Patent number: 7257006
    Abstract: An assembling electronic device includes a plurality of functional modules, a characterized casing having a plurality of receiving cavities, and a terminal circuit. Each of said functional modules is shaped and sized to detachably receive in the respective receiving cavity so as to securely retain the functional module in the characterized casing in position. The terminal circuit is provided at the characterized casing to electrically connect with the terminals of the functional modules when the functional modules are detachably received in the receiving cavities respectively so as to form a complete circuit for the functional modules, such that each of the functional modules is replaceably mounted in the characterized casing for enhancing a user-personalizability.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: August 14, 2007
    Inventor: Liang Sun
  • Patent number: 7254040
    Abstract: An apparatus, system, and method are disclosed for connecting and disconnecting daughter cards. A handle urges a locking member toward a base comprising a stop and a channel. The channel may direct the locking member to a specified position. The locking member biases the catch and the biased catch engages with the stop. The stop and the channel of the base secure the locking member to the base. In addition, the handle urges the locking member away from the base. The handle also urges an actuator to unbias the catch. The handle further disconnects the locking member from the base as the unbiased catch does not engage the stop.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: August 7, 2007
    Assignee: Lenovo Pte Ltd
    Inventors: Richard M. Barina, Norman Bruce Desroslers, Dean Frederick Herring, Paul Andrew Wormsbecher
  • Patent number: 7254038
    Abstract: A space-conscious system utilizes a low profile expansion card for providing a physical and electrical interface between a larger scale board, such as a motherboard, and an external component. The expansion card is mounted in a perpendicular orientation relative to the larger scale board, despite dimensional limitations with regard to such an orientation. The expansion card includes an input/output circuit board and a “signal-conduction extender” for enabling coupling to an external wall of the housing in which the expansion card and larger scale board are contained. In one possible embodiment, the housing is compatible with the 1U standard, the expansion card is an Ethernet card, and there is an adapter board at the front wall of the housing for routing connections from the expansion card to an exposed port. The invention allows a number of the expansion cards to be mounted in parallel within the same container.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 7, 2007
    Assignee: Barracuda Networks, Inc.
    Inventor: Dean M. Drako
  • Patent number: 7251142
    Abstract: The present invention discloses a timer switch that uses an integrated circuit to control the time and a self-locking electromagnetic coil solenoid valve to drive the operation of a microswitch, which is particularly applicable to be installed on a wall as a timer switch. The switch device uses the electronic control of two 1.5V AA batteries to enter a set time through input keys, and a CPU will issue a pulse with very short timing of 30 ms to the solenoid to produce a magnetic field to drive a turning rod and open a primary switch in order to turn on or off a circuit.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Timer Technologies Limited
    Inventor: David Ping Lai Lui
  • Patent number: 7248484
    Abstract: Embodiments of the present invention provide an electro-magnetic suppressive structure. The electro-magnetic suppressive structure comprises a cover portion and an integrally formed conductive portion.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: July 24, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Brooks, Mike Cherniski, Kevin Smith
  • Patent number: 7248138
    Abstract: The present invention provides an electromagnetic component formed from adjacent conducting layers of a multi-layer PCB and two additional conducting layers in contact with the PCB. The inventive component includes one or more winding turns formed by connecting the multiple layers of the multi-layer PCB with conductive vias and by connecting the additional conducting layers to respective top and bottom surfaces of the PCB. In one embodiment, one of the conducting layers is soldered to a top conducting layer of the PCB and the other of the conductive layers is soldered to a bottom conducting layer of the PCB, effectively increasing the cross-sectional area of the top and bottom winding layers. In another embodiment, the additional conducting layers are separated from the adjacent conducting PCB layers by a layer of insulation, permitting the additional conducting layers to form separate winding turns.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 24, 2007
    Assignee: Astec International Limited
    Inventors: Man-ho Chiang, Francois Lai Chung-hang
  • Patent number: 7248480
    Abstract: A semiconductor element comprises a capacitance variable section and an inductor section. In the capacitance variable section, a variable capacitance diode equipped with first and second control electrodes is provided on an insulative substrate. The inductor section is formed on the capacitance variable section formed with the variable capacitance diode. The inductor section is formed in an insulating layer provided on the variable capacitance diode. A first input/output electrode, a second input/output electrode, and first and second control input/output electrodes are provided in exposed form on the upper side of the insulating layer provided on the capacitance variable section.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Chiba
  • Patent number: 7245501
    Abstract: Circuit boards capable of receiving different sets of electrical devices are fabricated from raw boards of the same type by forming respective networks of electrically conductive traces with a common layout on the raw boards, including open circuits within the networks. Electrical device receivers and controllers are then loaded on the boards, and some of the open circuits are closed such that some of the boards have different patterns of closed circuits and thereby different interconnections. Some of the receivers can accommodate two different types of electrical devices, with some of the boards configured to support one type and the others another type. The loading of receivers and controllers, and the closing of open circuits, can be performed simultaneously with the placement of zero ohm resistors used for circuit closings. Numerous different circuit board configurations can thus be supported from a common supply of raw boards.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: July 17, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael A. Kotson, Robert A. Kubo
  • Patent number: 7245500
    Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted on a first surface of a stiffener. A first surface of a substrate is attached to a second surface of the stiffener that is opposed to the first surface of the stiffener. A bond pad of the IC die is coupled to a contact pad on the first surface of the substrate with a wire bond. The wire bond is coupled over a recessed step region in the first surface of the stiffener and through a through-pattern in the stiffener that has an edge adjacent to the recessed step region. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, or other through-pattern.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: July 17, 2007
    Assignee: Broadcom Corporation
    Inventors: Reza-ur Rahman Khan, Sam Ziqun Zhao
  • Patent number: 7245505
    Abstract: A laminated electronic component includes a laminated block in which a plurality of electrically insulating layers are laminated. An external conductor film is disposed on a surface of the laminated block. An additional conductor film which is at the same potential as the external conductor film is arranged such that it faces the external conductor film with an insulating layer disposed therebetween. The additional conductor film and the external conductor film are electrically connected to each other through a via-hole conductor so that they are at the same potential.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 17, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuhide Kato, Yoshikazu Chigodo, Keiji Ogawa
  • Patent number: 7245506
    Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: July 17, 2007
    Assignee: Dell Products L.P.
    Inventors: Stuart W. Hayes, Shane Chiasson
  • Patent number: 7242586
    Abstract: A small form factor transceiver module includes a cage (1) and a transceiver (2). The cage has a top wall (11), and two sidewalls (12) and a rear wall (13) integrally formed with the top wall. The transceiver received in the cage has a printed circuit board (3) and at least one optical-electric diode electrically connected to the printed circuit board. The sidewalls have two bottom boards (121), each with a flange (120). A plurality of pins (123, 125, 133) is integrally formed with and extends from the bottom boards, the sidewalls and the rear wall.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: July 10, 2007
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Yung Chang Cheng, Chung Hsing Mou
  • Patent number: 7242592
    Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: July 10, 2007
    Assignee: Amphenol Corporation
    Inventors: Jason J. Payne, Mark W. Gailus, Leon M. Khilchenko, Huilin Ren
  • Patent number: 7239528
    Abstract: Techniques for accommodating chassis tolerances use joiners which enable outer side panels for a front card cage to reference a front side of a midplane, and outer side panels for a rear card cage to reference a rear side of the midplane. The joiners couple the outer side panels together in a rigid but accommodating manner regardless of variations in midplane board thickness. Accordingly, both the front and rear card cages are capable of accurately and consistently referencing from the midplane sides. Not only do these techniques solve registration drawbacks which exist in conventional midplane installation approaches involving the bolting of midplanes to the middles of pre-constructed frames, these techniques further enable accurate direct connection of other components such as a power supply subsystem (e.g., to the midplane front side) and a fan assembly (e.g., to the midplane rear side) thus alleviating the need for burdensome cables.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: July 3, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Gary McLeod
  • Patent number: 7239529
    Abstract: A fixing member for fixing an auxiliary circuit board to a main circuit board is proposed. The fixing member includes a fixing portion for being fixed to the main circuit board; and a combining portion connected to the fixing portion. The combining portion can be elastically deviated from its original position by the auxiliary circuit board while electrically connecting the auxiliary circuit board to the main circuit board. The combining portion can then return back to its original position by its restoring force after the auxiliary circuit board is electrically connected to the main circuit board. Thus, the auxiliary circuit board and the fixing member are combined together, thereby firmly fixing the auxiliary circuit board to the main circuit board.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 3, 2007
    Assignee: Inventec Corporation
    Inventor: Lin-Wei Chang
  • Patent number: 7239524
    Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Chee-Yee Chung, Robert L. Sankman, Alex Waizman