Patents Examined by Tuan T. Lan
  • Selectable clock generation mode
    Patent number: 5926053
    Abstract: A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 20, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Mark W. McDermott, Antone L. Fourcroy