Abstract: A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes an image processor. The image processor includes an image signal processor having two or more processing elements. The processing elements concurrently process an array of pixel values via a plurality of image filter comparison operations.

Abstract: Data defining one or more graphic objects, such as buildings and vegetation, are automatically generated in a repeatable manner within each of a plurality of visual tiles of a simulated space. A seed is determined for a tile as a function of a location of the tile in the space. The seed is used to pseudo-randomly determine visually apparent characteristics of the graphic objects, such as position, height, and texture. A tile is preferably characterized by one or a combination of texture classes, such as vegetated and urban. Any tile can be associated with an annotation that specifies other characteristics of an object, such as its footprint, or of a sub-area within which objects will be depicted in the tile and rendered with the randomly determined characteristics. For multi-class tiles, the annotations are used to mask automatically generated graphic objects from undesired portions of the tile.

Abstract: Media composer for editing source material. The media composer includes apparatus for receiving digitizing, storing and editing video and audio source material. Computing apparatus manipulates the stored source material and output apparatus communicates with the computing apparatus to display the manipulated material and control information. The computing apparatus includes JPEG compression techniques and is programmed to provide enhanced editing features.

Abstract: A computer system and graphics controller which stores video data in memory corresponding to a plurality of video objects and presents the video objects on a video monitor, wherein a plurality of the video objects have differing numbers of bits per pixel formats. System memory stores video data in a plurality of memory areas for each of the plurality of video objects, wherein the plurality of video objects may have differing numbers of bits per pixel. The graphics controller obtains portions of the video data from the plurality of memory areas and in response provides video signals to the video monitor. The computer system and graphics controller performs pointer-based and/or display list-based video refresh operations that enable video object data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various areas or buffers in system memory comprising video or graphics display information.

Abstract: A system and method for a computer system to recognize and initialize an arrangement of a plurality of physical monitors as a single logical screen (SLS). The invention translates a user's window operation request directed to the SLS into an SLS function. The SLS function is then translated into a plurality of device dependent functions, each of which performs the user's requested window operation on one physical monitor. The translation of the SLS function comprises an unwrapping of the SLS function by removing the SLS function and installing the plurality of device dependent functions, and the wrapping of the plurality of device dependent functions by removing the plurality of device dependent functions and installing the SLS function. The invention implements each of the unwrapping and wrapping operations in two assignment instructions.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ("FC-AL") interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP/ FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

Abstract: Method and apparatus for selecting samples for presentation on an output device, such as a display or speaker, from a sequence of stored media samples, such as audio or video information. Position information is received from a pointing device, such as a mouse, and translated into direction and magnitude information. A second sample is then retrieved based on this position and magnitude information. This method may be used to implement jog or shuttle controls for a media composer, which may be provided with simulated "inertia" for ease of use.

Abstract: This invention relates to a video graphic control method and controller for sending to a display device graphic data from a processing device, and the object thereof is to provide a video graphic controller that increases the bandwidth available to a graphic engine or CPU without increasing power consumption or manufacturing costs, even when used with a conventional frame memory. A video graphic controller for controlling video data by storing the video data from a CPU 4 in a frame memory 18 and causing the frame memory 18 to output the data to a display device 30 uses a video data comparison means 20 to compare a piece of video data stored in the N-th address of the frame memory 18 to another piece of video data stored in the N-1-th address in order to determine whether the two pieces of data match, and if the two pieces of data match, outputs to the display device 30 the piece of video data stored in the N-1-th address instead of the piece of video data stored in the N-th address.

Abstract: An integrated memory controller (IMC) which incorporates novel memory, graphics, and audio processing capabilities in a single logical unit. The IMC includes numerous significant advances which provide greatly increased performance over prior art systems. The integrated memory controller (IMC) includes one or more symmetric memory ports for connecting to system memory. The IMC also includes video outputs, preferably RGB (red, green, blue) outputs as well as horizontal and vertical synchronization signal outputs, to directly drive the video display monitor. The IMC transfers data between the system bus and system memory and also transfers data between the system memory and the video display output, thereby eliminating the need for a separate graphics subsystem. The IMC also improves overall system performance and response using main system memory for graphical information and storage.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: A method for drawing graphics is carried out in a graphics processing and display system. The system has a display unit, a host for generating graphics data defining graphics images to be displayed on the display, a graphics controller for receiving information from the host and controlling graphics to be displayed, a frame buffer memory for storing graphics data, an index register for receiving an index value from the host and a coordinate register for storing a coordinate value which is obtained by the graphics controller. With the method, when a line graphics is draw, only information regarding two coordinates are used in the graphics controller by incrementing the index value by an increase which is specified according to the selected object-type. When a triangle graphics is drawn, only information regarding three coordinates are used in the graphics controller.

Abstract: An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an audio processor, a video processor and a memory controller. Each of the modules gains control over the data bus via arbitration by the memory controller for accessing the memory. The access priority of the CPU to the data bus is maintained at a relatively lower level except when the CPU needs to perform parsing on the MPEG compressed data and implementing the initial decoding of the audio compressed data. The use of data bus bandwidth is therefore balanced among all the system resources thereby increasing the overall system performance.

Abstract: According to the present invention, provided are a list generator for generating, upon receipt of a printer command from a host computer, a display list that serves as intermediate code that printers use in common, a storage section for storing, in advance, an estimated drawing time for each object, which is required for drawing a raster image of the display list, a determination section for ascertaining, before drawing of the raster image for each band width is begun, whether or not an estimated drawing time for the display list is stored in the storage section, and a controller for calculating a drawing time by the addition of the estimated drawing time for the display list when the determination section ascertains that the estimated drawing time is stored, and for performing a predetermined calculation to acquire a drawing time that is required for developing the display list into a raster image when the determination section ascertains that the estimated drawing time is not stored.

Abstract: An electronic video processing system comprises a store (11) for storing data defining plural video clips, and a processor (21, 27, 28, 29) for selecting from the stored video clips a plurality of clips and for selectively combining data defining the selected clips to form data defining a video story. A plurality of representative frames respectively representing selected video edits is displayable to portray a portion of the video story. Also, for each selected clip, a frame representative thereof is displayable together with a pair of smaller frames derived from the first and last frames of the clip.

Abstract: Memory addressing apparatus and method for block scan and raster scan in an apparatus for processing image data of which the horizontal resolution is H and the vertical resolution is V. The memory addressing apparatus includes a horizontal counter for outputting a value sequentially incremented by a write or read signal for storing or reading image data in or from the memory, a vertical counter for outputting a value sequentially incremented by a horizontal synchronizing signal included in the image data, and an address generator for generating an address for raster scan or block scan according to a control signal by the horizontal and the vertical count values. Accordingly, memory address generating functions for raster scan and block scan are integrated into one unit, thereby the amount of required hardware is reduced, and simple design and structure of the apparatus reduce manufacturing cost.

Abstract: A method and system for remote control of a target computer by a controller computer through a network. The graphic commands issued by the graphic engine of the target computer are "hooked" and translated into a system independent format. The translated commands are then transmitted to the controller computer to be replayed on the display. The independency from the operating system is realized by defining a protocol which is used to translate a subset of the graphic commands in the target computer before the transmission to the controller computer where the commands are re-translated according to the same protocol.

Abstract: In a system for displaying prices in a retail store, an improved protocol is disclosed to permit improved communications between a host, or central computer and display devices. Such a protocol enables the host to effectively communicate messages to the display devices for the latter to display information to consumers and/or store personnel.

Abstract: A storage device and access method for performing hierarchical coding without the need for employing a circuit for a line delay, in addition to a memory for storing an image. An address providing circuit provides a 9-bit horizontal address and a 9-bit vertical address, as an address, to a first layer memory while providing, to a second layer memory, higher order eight bits of the horizontal address and the vertical address without respective least significant bits. As a result, at the timing each of the pixels in the first layer is written on each of addresses (2s,2t), (2s+1,2t), (2s,2t+1) and (2s+1,2t+1) in the first layer memory, the same address (s,t) in the second layer memory is accessed. Taking advantage of this, a read-modify-write circuit determines the sum of storage values at addresses (2s,2t), (2s+1,2t), (2s,2t+1), and (2s+1,2t+1) in the first layer memory and writes the sum onto the address (s,t) in the second layer memory.

Abstract: A memory system 107,300 is provided which includes a memory 107 having a data area for storing data words and a mask area 302 for storing a control mask. Mask generation circuitry 301 is provided for generating such a control mask for storage in the mask area 302 of the memory 107. Mask controlled memory read control circuitry 303 is provided which is operable to selectively retrieve from the mask area 302 bits of the mask stored therein and in response selectively retrieve and output data words stored in the data area of the memory 107.