Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.

Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.

Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a first sensing operation corresponding to a first sensing voltage to generate a first digital value of the Flash cell; according to a result of the first sensing operation, performing a plurality of second sensing operations to generate a second digital value of the Flash cell representing at least one candidate threshold voltage of the Flash cell; determining the threshold voltage of the memory Flash cell according to the at least one candidate threshold voltage; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

Abstract: In a method of programming a memory device, inhibit information is stored to first latch structures and second latch structures. A first state programming voltage is applied to data lines of memory cells of the memory device to program the memory cells to the first state. A first state verification voltage is applied to the data lines of the memory cells to perform a first state verification operation on the memory cells. The first state verification operation verifies first state threshold voltages of the memory cells based on a first target value and also generates failure pattern data of the first state verification operation. The failure pattern data is then stored to the second latch structures. Further, a first level adjusted verification voltage is applied to the data lines of a portion of the memory cells that fails the first level verification operation to perform a first level adjusted verification operation.

Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a memory controller. The non-volatile memory includes memory blocks each including a word lines. The memory controller determines a word line strength of each of the word lines, adjusts a state count of each of the word lines based on the word line strengths, and adjust a program parameter of each of the word lines to decrease a program time variation between the word lines.