Abstract: A system and method for generating and transmitting false packets along with a true packet to thereby hide or obscure the actual message traffic. A new extension header having a plurality of fields is positioned in the hierarchy of Internet protocol headers that control passage of the false packets and the true packet through the network. A sending host computer generates a plurality of false packets for each true packet and transmits the false packets and the true packet containing the Internet protocol headers and the extension header over the network. The new extension header is decrypted and re-encrypted each host that handles a message packet that uses the new extension header to control the random re-encryption of the true packet body at random hosts and the random generation of false packets at each host visited by a true packet, at the recipient of the true packet, and at any hosts that receive a false packet.

Abstract: A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.

Abstract: A semiconductor stack including a base member and a semiconductor assembly member provided on the base member. The semiconductor assembly member includes a switching element having a first, a second and a third terminal, mounted on a surface of the base member such that the first, second and third terminals of the switching element are led to a same plane, and a batch laminated conductor positioned on the first, second and third terminals of the switching element, composed of superimposition of a first, a second and a third conductor and insulators for insulating between adjacent two of the conductors. The semiconductor assembly member also includes a first, a second and a third connecting device for connecting the first, second and third conductors and the first, second and third terminals of the switching element, respectively.

Abstract: A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left therebetween and covered with the semiconductor film. The gate isolating film is over the part of the first semiconductor layer and is made of either an insulating material or a semiconductor material, each of which materials should have a wider forbidden bandwidth than a semiconductor material of the semiconductor film, such as silicon dioxide, silicon nitride, or aluminium nitride, or gallium phosphide for silicon, or AlGaAs fox gallium arsenide. A source electrode is formed on an uncovered area of the first semiconductor layer. The semiconductor film forms a tunnel junction with the first semiconductor layer and an ohmic junction with the second semiconductor layer, which junction may be either a homojunction or a heterojunction.

Abstract: There is disclosed a field effect transistor having a channel layer, an electron supply layer, and a spacer layer formed between the channel layer and the electron supply layer. The spacer layer has a thickness for spatially separating a two-dimensional electron gas from donor ions in the electron supply layer, and for forming the two-dimensional electron gas in the channel layer by the Coulomb force of the donor ions. The spacer layer material has better high frequency characteristics than that of the electron supply layer.

Abstract: A protective device for protecting a CMOS circuit included in an internal circuit of an IC against overvoltage applied to a power source wiring and preventing the CMOS from being latched-up by surge voltage due to external noise during a normal operation of the IC is disclosed. An N channel MOS FET and a P channel MOS FET are arranged in parallel to each other and connected between a power source wiring and a ground wiring. Gate electrodes of the N channel and the P channel MOS FETs are connected to the ground wiring and the power source wiring, respectively. Positive overvoltage or surge voltage applied to the power source wiring is relieved by breakdown of drain junctions of both the MOS FETs.

Abstract: A semiconductor memory device capable of being electrically written and erased comprising a floating gate, wherein, a silicon nitride, silicon oxinitride, aluminum oxide, or silicon carbide film is incorporated between the drain region and the floating gate.

Abstract: The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

Abstract: A double diamond mesa vertical field effect transistor includes a diamond layer, a first diamond mesa on a diamond layer, and a second diamond mesa on the first diamond mesa, opposite the diamond layer. A source contact is formed on the second diamond mesa, opposite the first diamond mesa, and a gate is formed on the first diamond mesa opposite the diamond layer. The drain contact may be formed on the diamond layer adjacent the first diamond mesa, or the diamond layer itself may be formed on a nondiamond substrate and a drain contact may be provided on the nondiamond substrate. An integrated array of field effect transistors may be formed, including a plurality of second mesas on the first mesa, with a plurality of gates formed on the first mesa between the second mesas and a source formed on each second mesa, opposite the first mesa. The second mesas may also extend over the multiple gate contacts on the first mesa to form a common source region with a common source contact.

Abstract: A DRAM having memory cells each consisting of a MOS transistor and a trench-stack capacitor built at a p-type silicon substrate. The MOS transistor comprises a source region made of the first diffused n.sup.- layer, and a drain region composed of the first diffused n.sup.- layer and the first diffused n.sup.+ layer self-aligned with respect to a bit contact hole. At the surface of the p-type silicon substrate is formed a trench penetrating through the source region near the gate electrode of the MOS transistor working also as a word line. The capacitor is built to extend deep into a U-shaped section. The second diffused n.sup.- layer is formed at the the trench sidewall surface of the p-type silicon substrate, and the second insulating film is formed over the sidewall of the trench. The second diffused n.sup.+ layer is formed at the trench bottom surface of the p-type silicon substrate. The bottom face of the trench functions as a node contact hole of the memory cell.

Abstract: A semiconductor chip carrier has a first substrate and at least one second substrate. The first substrate is for carrying at least one semiconductor chip of integrated circuits. The first substrate has predetermined functional elements for connection to the integrated circuits of the at least one semiconductor chip. Such a second substrate is directly coupled to the first substrate. The second substrate is capable of being independently created and has predetermined electrical functional elements for connection to the integrated circuits of the semiconductor chip. The electrical functional elements of each second substrate are of one type and are different than the electrical functional elements of the other second substrates and the first substrate.

Abstract: There is provided a high-speed heterojunction transistor which is excellent in heat and radiation resistances with its emitter injection efficiency improved due to heterojunction. A .beta. silicon carbide layer (44) acting as base region is grown on an .alpha. silicon carbide substrate (42) acting as emitter region. Due to the difference in forbidden band between the .alpha. silicon carbide substrate (42) and the .beta. silicon carbide layer (44), heterojunction can be obtained. Because the .alpha. silicon carbide substrate (42) has a wider forbidden band, emitter efficiency is improved, allowing a high-speed transistor to be realized. Further, the device is made of silicon carbide, it is excellent in heat and radiation resistances. This invention may be used in an embodiment in which a heterojunction bipolar transistor or a heterojunction IIL is manufactured.

Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

Abstract: An opto-electronic device with the physical and chemical characteristics at the junction thereof being well matched is disclosed. The opto-etectronic device includes a wafer, a first layer grown on the wafer, and a second layer grown on the first layer, wherein one of the first and second layers is an ordered structure while the other is a disordered structure.

Abstract: A ferroelectrics device includes a semiconductor substrate having a diamond structure or zinc blend structure, and a ferroelectric compound film formed on the semiconductor substrate by selective epitaxial growth. The ferroelectric compound film is made of a mixed crystal of at least three components in groups II and VI and has the same structure as the semiconductor substrate.

Abstract: A semiconductor device comprising a capacitor which comprises a lower electrode, a dielectric insulating film of a metal oxide, and a upper electrode. The lower electrode is made of at least yttrium (Y) or hafnium (Hf).

Abstract: In a thick multilayered wiring board, a coaxial signal wiring pattern is surrounded by upper and lower horizontal grounded conductive layers and vertical grounded conductive layers and the vertical conductive layers of conductive layers which surround the coaxial signal wiring pattern are formed in a photosensitive dielectric layer by a photolithography, whereby matching of characteristic impedance of the pattern is improved and thus crosstalk is reduced.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: A light emitting diode including a carrier injection layer of semiconductor material, such as diamond, and a light emitting layer of electroluminescent organic material, such as PPV, positioned to form a diode junction therebetween. The semiconductor material being selected to have a wider bandgap than the organic material and the materials being further selected to minimize the discontinuities at the junction which would cause energy spikes.

Abstract: A semiconductor device having an electrode wiring which prevents generation of hillock and has good stress migration capability is disclosed. A multi layer film including at least two Al-Si-Cu alloy films and at least two titanium nitride films formed by reactive sputtering laminated alternately with the Al-Si-Cu alloy films has a high mechanical strength against deformation and can effectively prevent generation of hillock. Ti-Al intermetallic compounds are formed in grain boundaries and in interfaces, which is effective to restrict generation of a void. Propagation of a void can be prevented by the intermediate titanium nitride film. Further, the formation of the Ti-Al compounds is restricted and an increase of resistance is negligible.