Patents Examined by Valenica Martin Wallace
  • Patent number: 5763910
    Abstract: The present invention relates to a semiconductor device whose through-holes are formed by self-alignment and a method for fabricating the same. The through-holes formed on the gate electrodes can be formed simultaneously with SACs without complicating the fabrication process. The semiconductor device comprises a semiconductor substrate, a device isolation film defining devices regions on the semiconductor substrate, a pair of diffused layers formed in the device regions, gate electrodes formed through a first insulation film on the semiconductor substrate between the pair of diffused layers, and an etching stopper film covering side walls of the gate electrodes and parts of top surfaces of the gate electrodes which are extended inward by a prescribed distance from peripheral edges thereof. Whereby through-holes of an SAC structure can be formed in a later step, and the through-holes can be formed to expose the gate electrodes without removing the etching stopper film.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: June 9, 1998
    Assignee: Fujitsu Limited
    Inventor: Taiji Ema