Patents Examined by Valerie N Newton
-
Patent number: 11978756Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
-
Patent number: 11941485Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.Type: GrantFiled: November 24, 2021Date of Patent: March 26, 2024Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
-
Patent number: 11910627Abstract: An organic light-emitting device an improved anode structure and an organic electroluminescent display device using the same are provided. The anode structure has a 3 layers stack structure in which a layer closest to an organic light-emissive layer of the organic light-emitting device is made of a material with a high work function such as 5.1 to 5.3 eV. Thus, hole injection efficiency is improved and occurrence of dark spots is suppressed.Type: GrantFiled: September 3, 2021Date of Patent: February 20, 2024Assignee: LG Display Co., Ltd.Inventors: Changeun Kim, Sujeong Lee
-
Patent number: 11869947Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.Type: GrantFiled: May 3, 2021Date of Patent: January 9, 2024Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
-
Patent number: 11864431Abstract: A light emitting display device includes a lower substrate, a driving transistor positioned on the lower substrate and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and a light shield layer covering a lower surface, an upper surface, and a side surface of the semiconductor layer, for protecting the driving transistor from external light.Type: GrantFiled: December 16, 2020Date of Patent: January 2, 2024Assignee: LG Display Co., Ltd.Inventor: Mi-Ae Kim
-
Patent number: 11837461Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: GrantFiled: September 2, 2020Date of Patent: December 5, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
-
Patent number: 11830915Abstract: A nitride semiconductor device includes a GaN-based semiconductor layer; and an insulating film provided on a first surface of the GaN-based semiconductor layer, the insulating film containing O atoms, and other constituent atoms other than O. An interface between the GaN-based semiconductor layer and the insulating film has a terminating species which terminates a dangling bond of a Ga atom, the terminating species has an outermost electron shell in which one electron is deficient from an allowed number of outermost electrons, and is an atom or molecule having stronger bond to the Ga atom than a H atom, an amount of Ga—O bonds is greater than an amount of bonds between the Ga atoms and the other constituent atoms.Type: GrantFiled: February 26, 2021Date of Patent: November 28, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuki Ohuchi, Katsunori Ueno
-
Patent number: 11742403Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, and an insulating part region. The second electrode includes a first electrode portion. The semiconductor member includes a first semiconductor region. The first semiconductor region includes first to third partial regions. The first partial region is between the first electrode and the first electrode portion. The second partial region is between the first and third electrodes. The third partial region is between the first partial region and the first electrode portion. The third partial region includes first and second positions. The second position is between the first partial region and the first position. The first conductive member includes first and second portions. The first portion is between the second partial region and the third electrode. The insulating part region includes first and second insulating regions.Type: GrantFiled: August 11, 2021Date of Patent: August 29, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Hiro Gangi, Yusuke Kobayashi, Hiroki Nemoto
-
Patent number: 11730002Abstract: A display device includes a first bank and a second bank spaced apart from each other on a substrate, at least one semiconductor layer disposed between the first bank and the second bank, a first electrode disposed on the first bank and electrically connected to a part of the at least one semiconductor layer, an organic functional layer disposed on another part of the semiconductor layer and comprising at least an organic light emitting layer, and a second electrode disposed on the organic functional layer.Type: GrantFiled: July 22, 2021Date of Patent: August 15, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Je Won Yoo, In Hyuk Kim
-
Patent number: 11728410Abstract: A semiconductor device includes a substrate having a trench, a conductive pattern in the trench, a spacer structure on a side surface of the conductive pattern, and a buried contact including a first portion apart from the conductive pattern by the spacer structure and filling a contact recess, and a second portion on the first portion having a pillar shape with a width smaller than that of a top surface of the first portion. The spacer structure includes a first spacer extending along the second portion of the buried contact on the first portion of the buried contact and contacting the buried contact, a second spacer extending along the first spacer, and a third spacer extending along the side surface of the conductive pattern and the trench and apart from the first spacer by the second spacer, the first spacer includes silicon oxide, and the second spacer includes silicon nitride.Type: GrantFiled: June 4, 2021Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jin A. Kim, Ho-In Ryu, Jae Won Na
-
Patent number: 11723223Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.Type: GrantFiled: January 26, 2021Date of Patent: August 8, 2023Assignee: BAE Systems Imaging Solutions Inc.Inventor: Robert Daniel McGrath
-
Patent number: 11723240Abstract: A display panel includes a first display area including first light emitting areas and a second display area adjacent to the first display area and including second light emitting areas and a signal transmission area; a base substrate; a circuit element layer disposed on the base substrate; a light blocking pattern disposed between the base substrate and the circuit element layer, overlapping the first and second light emitting areas, and having a first opening corresponding to the signal transmission area; and a light emitting element layer disposed on the circuit element layer and including a first electrode overlapping the first and second light emitting areas, a light emitting layer disposed on the first electrode, and a second electrode overlapping the first and second light emitting areas. The signal transmission area has a second transmittance that is higher than a first transmittance of the second light emitting areas.Type: GrantFiled: January 13, 2021Date of Patent: August 8, 2023Assignee: Samsung Display Co., Ltd.Inventors: Eon Seok Oh, Woosik Jeon, Jungmin Choi, Junkyeong Jeong, Seungsoo Hong
-
Patent number: 11710662Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.Type: GrantFiled: September 23, 2020Date of Patent: July 25, 2023Assignee: United Silicon Carbide, Inc.Inventors: Anup Bhalla, Leonid Fursin
-
Patent number: 11699750Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.Type: GrantFiled: October 1, 2020Date of Patent: July 11, 2023Assignee: QROMIS, INC.Inventors: Vladimir Odnoblyudov, Steve Lester, Ozgur Aktas
-
Patent number: 11696464Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a display area and a hole forming area, where the display area surrounds the hole forming area, and an organic material layer is provided in the hole forming area so that a height difference between the hole forming area and the display area is less than a threshold value of 4 um.Type: GrantFiled: July 10, 2020Date of Patent: July 4, 2023Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xuwu Hu, Yangsheng Liu, Mengxia Kong, Yuheng Qiu, Wei Lin
-
Patent number: 11688783Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.Type: GrantFiled: December 7, 2021Date of Patent: June 27, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Lin Hsiao
-
Patent number: 11682689Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: June 20, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
-
Patent number: 11682593Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: July 20, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
-
Patent number: 11677002Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.Type: GrantFiled: September 16, 2020Date of Patent: June 13, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Chih-Hung Lin, Po-Heng Lin
-
Patent number: 11677007Abstract: A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.Type: GrantFiled: February 10, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Amit Kundu, Jaw-Juinn Horng