Patents Examined by Vicki B Booker
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Patent number: 11978668Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.Type: GrantFiled: December 9, 2021Date of Patent: May 7, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ming He, Harsono Simka, Anthony Dongick Lee, Seowoo Nam, Sang Hoon Ahn
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Patent number: 11978705Abstract: A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions.Type: GrantFiled: December 7, 2021Date of Patent: May 7, 2024Assignee: Micron Technology, Inc.Inventors: Shuangqiang Luo, Lifang Xu, Xiao Li, Jivaan Kishore Jhothiraman, Mohadeseh Asadolahi Baboli
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Patent number: 11978763Abstract: An electrical device that includes a substrate; a 3D capacitor including a capacitor dielectric region of a dielectric material, a capacitor electrode region of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity extending in the substrate from a top face of the substrate; and a surrounding through opening in the substrate and which surrounds a surrounded substrate region, the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to a bottom face of the substrate, wherein inside the surrounding through opening a surrounding dielectric region of the dielectric material and a surrounding conductive region of the conductive material are arranged.Type: GrantFiled: December 15, 2021Date of Patent: May 7, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Stéphane Bouvier, Nicolas Normand, Emmanuel Lefeuvre
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Patent number: 11955430Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.Type: GrantFiled: March 31, 2021Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hsuan Lin, Hsi Chung Chen, Ji-Ling Wu, Chih-Teng Liao
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Patent number: 11942429Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Memory openings, contact via cavities, or backside trenches may be used as access points for removing the sacrificial material layers.Type: GrantFiled: June 18, 2021Date of Patent: March 26, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Tatsuya Hinoue, Naoki Takeguchi, Masanori Tsutsumi, Seiji Shimabukuro
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Patent number: 11929281Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.Type: GrantFiled: September 21, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
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Patent number: 11929280Abstract: A contact window structure and a method for forming the contact window structure are provided. The method includes: an etching spacer is formed on a surface of a target layer, and a dielectric layer covering a substrate, the target layer and the etching spacer is formed; the dielectric layer is etched to form an etching hole in the dielectric layer, a bottom of the etching hole exposing a top surface of the etching spacer; and the etching spacer is removed along the etching hole to form an etching channel communicating with the etching hole, the etching channel exposing a portion of the surface of the target layer and constituting a contact window structure with the etching hole.Type: GrantFiled: August 9, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ping-Heng Wu
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Patent number: 11923246Abstract: A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.Type: GrantFiled: September 15, 2021Date of Patent: March 5, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Koichi Motoyama, Dominik Metzler, Ekmini Anuja De Silva, Chanro Park, Hsueh-Chung Chen
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Patent number: 11923300Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.Type: GrantFiled: July 9, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Ken-Hsien Hsieh
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Patent number: 11915975Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.Type: GrantFiled: September 21, 2021Date of Patent: February 27, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya Yoshida, Tomohiro Tomizawa
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Patent number: 11915966Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.Type: GrantFiled: June 9, 2021Date of Patent: February 27, 2024Assignee: International Business Machines CorporationInventors: Ruilong Xie, Takeshi Nogami, Roy R. Yu, Balasubramanian Pranatharthiharan, Albert M. Young, Kisik Choi, Brent Anderson
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Patent number: 11908731Abstract: A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.Type: GrantFiled: July 9, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Tse Lai, Ya Hui Chang
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Patent number: 11908974Abstract: A light emitting device (LED) includes an n-doped semiconductor material layer, an active region including an optically active compound semiconductor layer stack configured to emit light located on the n-doped semiconductor material layer, a p-doped semiconductor material layer located on the active region, an anode contact contacting the p-doped semiconductor material layer, a reflector overlying and electrically connected to the anode contact, and a device-side bonding pad layer located on the reflector. The p-doped semiconductor material layer includes an electrically active region that is at least partially covered by the anode contact and an inactive region that an electrical conductivity less than 30% of the electrically active region.Type: GrantFiled: January 25, 2022Date of Patent: February 20, 2024Assignee: GLO TECHNOLOGIES LLCInventors: Max Batres, Fariba Danesh, Michael J. Cich, Zhen Chen
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Patent number: 11903204Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.Type: GrantFiled: April 25, 2022Date of Patent: February 13, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Haojie Song, Kun Bao, Zhiliang Xia
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Patent number: 11901228Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.Type: GrantFiled: July 9, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
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Patent number: 11901221Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.Type: GrantFiled: June 1, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
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Patent number: 11901180Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.Type: GrantFiled: February 14, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11901287Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.Type: GrantFiled: September 15, 2021Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Shuangqiang Luo, Lifang Xu
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Patent number: 11901454Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.Type: GrantFiled: June 21, 2022Date of Patent: February 13, 2024Assignee: Sony Group CorporationInventor: Yasushi Tateshita
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Patent number: 11901434Abstract: In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.Type: GrantFiled: April 30, 2021Date of Patent: February 13, 2024Assignee: QUALCOMM IncorporatedInventors: Junjing Bao, Haining Yang, Youseok Suh