Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.

Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.

Abstract: A chip-scale packaging process for wafer-level camera manufacture includes aligning an optics component wafer with an interposer wafer having a photoresist pattern that forms a plurality of transparent regions, bonding the aligned optics component wafer to the interposer wafer, and dicing the bonded optics component wafer and interposer wafer such that each optics component with interposer has a transparent region. The process further includes dicing an image sensor wafer, aligning the pixel array of each image sensor with the transparent region of a respective optics component with interposer, and bonding each image sensor to its respective optics component with interposer. Each interposer provides alignment between its respective optics component center and its respective pixel array center of the image sensor based on the respective transparent region. The interposer further provides a back focal length for focusing light from the optics component onto a top surface of the pixel array.

Abstract: A flange on first open end of a tubular contact member is soldered to a conductive plate of an insulating substrate. An external electrode terminal is fitted into a main body tube portion of the tubular contact member. The tubular contact member includes a protrusion that protrudes inwardly from an inner wall of the main body tube portion. The protrusion is disposed along the entire perimeter of inner wall toward the first open end. The protrusion has a thickness deformation of the protrusion by a load applied thereto when the external electrode terminal is pressed into the main body tube portion. The protrusion is disposed at a height that can block solder that climbs the inner wall of the main body tube portion, to form a gap between the protrusion and a lower end of the external electrode terminal inserted to a predetermined depth of the main body tube portion.

Abstract: An optoelectronic module includes a cover substrate including a passive optical element, a base substrate including an optoelectronic device, and a spacer layer joining the cover substrate to the base substrate. The spacer layer includes multiple first spacer elements fixed to a surface of the cover substrate and multiple second spacer elements fixed to a surface of the base substrate, in which each first spacer element is joined to a corresponding second spacer element through an adhesive layer, and in which the cover substrate, base substrate, and spacer layer define an interior region of the module in which the optical element is aligned with the optoelectronic device.

Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.

Abstract: A cell comprising at least one diffusion region and a plurality of interconnection conductive patterns located over the at least one diffusion layer and comprising a first outer interconnection conductive pattern and a second outer interconnection conductive pattern. The cell further includes at least one different conductive pattern located above the at least one diffusion region and interspersed between the plurality of interconnection conductive patterns. The at least one diffusion region extends in a first direction and the plurality of interconnection conductive patterns and at least one different conductive pattern extend in a second direction substantially perpendicular to the first direction.

Abstract: A semiconductor device manufacturing method includes forming a plurality of semiconductor chips on a main surface of a semiconductor wafer, electrically testing each of the semiconductor chips, dicing the semiconductor wafer into individual semiconductor chips and assembling each of the semiconductor chips into a package to be a semiconductor device, subjecting the packages to a burn-in test, determining whether each of the semiconductor chips requires the burn-in test to be performed, and generating a determination model for determining whether the semiconductor chips require the burn-in test to be performed.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Abstract: A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die. The power grid layers have power rails. First and second metal plates are formed in metal layers of the die between the power grid layers. Full vias extend from a power rail of the first polarity of the first power grid layer to a first side of the second metal plate and from a second side of the second metal plate opposite the first side of the metal plate to a power rail of the first polarity of the second power grid layer. Partial vias extend from the power rail of the first polarity of the second power grid layer and end at the second side of the second metal plate.

Abstract: A display device includes: a scan line extending in a first direction; first, second and third signal lines extending in a second direction; a first sub-pixel connected to the scan line and the first signal line; a second sub-pixel connected to the scan line and the second signal line; and a third sub-pixel connected to the scan line and the third signal line. The second signal line disposed between the first sub-pixel and the third sub-pixel is formed by a different layer so as to overlap with the third signal line as viewed in a plan view.

Abstract: Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate, a p-well formed in the semiconductor substrate, and an n-well formed in the semiconductor substrate and isolated from the p-well. The MTP memory cell further includes a p-channel transistor disposed over the n-well and including a transistor gate. Also, the MTP memory cell includes a p-channel capacitor disposed over the p-well and including a capacitor gate. The capacitor gate is coupled to the transistor gate.