Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: In a storage apparatus and its control method including multiple first virtual volumes to be provided to a host system and multiple pools each having a memory capacity, and equipped with a function of dynamically allocating a storage area to the first virtual volumes from the pools associated with the first virtual volumes in accordance with the usage status of the first virtual volumes, the unused capacity in each of the pools is managed, and, when the unused capacity of one of the pools falls below a predetermined threshold value, a part of the unused capacity of the other pools is allocated to the one pool. It is thereby possible to realize a highly reliable storage apparatus and its control method.

Abstract: A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory.

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract: A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks.

Abstract: The present invention relates to a methodology and computer program product for data storage migration that comprises monitoring a plurality of entities that comprise a storage area network for a predetermined set of information gathering cycles, constructing a resource graph that is representative of the entities that are comprised within the storage area network, and analyzing the resource graph. Further comprised are the determining of a data storage source and a data storage target for the migration of data stored at the data storage source, determining a time period and an execution point for the migration of the stored data, determining a data migration schedule, migrating the stored data according to the determined data migration schedule, and monitoring the data migration operation until the completion of the data migration operation.

Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.

Abstract: A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system cache. The building includes designating a number of sub-entries for each entry which is determined by a number of sub-entries operable for performing system cache coherency functions. The building also includes providing a sub-entry logic designator for each entry, and mapping one of the sub-entries for each entry to the system cache via the sub-entry logic designator.

Abstract: Methods and apparatuses provide a multi-level buffer cache having queues corresponding to different priority levels of queuing within the buffer cache. One or more data blocks are buffered in the buffer cache. In one embodiment, an initial level of queue is identified for a data block to be buffered in the buffer cache. The initial level of queue can be modified higher or lower depending on a value of a cache property associated with the data block. In one embodiment, the data block is monitored for data access in a queue, and the data block is aged and moved to higher level(s) of queuing based on rules for the data block. The rules can apply to the queue in which the data block is buffered, to a data type of the data block, or to a logical partition to which the data block belongs.

Abstract: A portable multifunction computing device optimizes cache storage when processing media files and the like. During a playback operation, the device caches as many media items as possible such that during playback media items are retrieved from cache rather than from a hard disk memory. The device monitors memory requirements of other programs and applications currently in use on the device to insure sufficient cache memory is available for such programs and applications.

Abstract: There is disclosed a data storage system used in a computer environment where there are plural host computers and plural storage array controllers. When a remote copy is made while assuring the order of writing across plural storage array controllers, one of the host computers gains copy information about all the storage array controllers associated with the remote copy as a representative. The representative one of the storage array controllers collects and stores copy statuses which are individually managed by the storage array controllers for which a remote copy is made. The host computer gains the copy statuses from the representative controller using an instruction to gain the copy statuses.

Abstract: Provided is a storage controller that will not impair the operation of a storage control system even when a new storage area is added to a pool corresponding to an AOU volume. This storage controller includes a logical volume accessible by a host system; a pool associated with the logical volume and including one or more physical storage areas configuring a storage area of the logical volume; and a memory for storing attribute information showing an attribute of a physical storage area included in the pool; wherein the controller is configured to add a new physical storage area to the pool based on the attribute information.

Abstract: The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads (5, 6, 7) are associated with a respective data structure (9, 10, 11) comprising a number of bits (12) that correspond to memory elements (m0, m1, m2, mn) of a shared memory (4). When a thread accesses a memory element in the shared memory, it sets a bit in its associated data structure, which bit corresponds to the accessed memory element. This indicates that the memory element has been accessed by the thread. Collision detection may be carried out after the thread has finished executing by means of comparing the data structure of the thread with the data structures of other threads on which the thread may depend.

Abstract: The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.

Abstract: Method and apparatus for using block level quality of service (QOS) data in a data storage device. A memory space is provided with a plurality of physical data storage blocks, such as data sectors on a magnetic disc. The QOS data identify at least one QOS characteristic for each of the available blocks. Transfers of user data between the blocks and a host device are preferably carried out in relation to the QOS data. In some preferred embodiments, the QOS data identifies a certification state for each of the blocks. In this way, the device is manufactured with less than all of the blocks having been successfully certified, and the remaining blocks are certified by the device during field use. In other preferred embodiments, the QOS data include a virus scan status, an access history, a write status, or an overlapped track indication for each said block.

Abstract: There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.

Abstract: The storage system is coupled to a computer, and includes a controller and a disk drive including a plurality of logical volumes, at least in one of which updating prohibition information indicating inclusion of an area assigned an updating prohibition attribute is recorded. The controller includes a configuration management module that sets the logical volume assigned the updating prohibition attribute as a logical volume of a migration source, another logical volume as a logical volume of a migration destination, and the updating prohibition information concerning the logical volume of the migration source in the logical volume of the migration destination, and a migration module that copies data of the logical volume of the migration source to the logical volume of the migration destination after the setting of the updating prohibition information concerning the logical volume of the migration source in the logical volume of the migration destination.