Abstract: A method for avoiding livelocks due to colliding writebacks within a NUMA computer system is disclosed. The NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to an attempt by a processor located at a home node to access a modified cache line at a remote node via a memory request at substantially the same time when a processor located at the remote node attempts to writeback the modified cache line to the home node, the writeback is allowed to complete at the home node without retry only if the writeback is from what a coherency directory within the home node considered as an owning node of the modified cache line. The memory request is then allowed to retry and completed at the home node.

Abstract: A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache memories associated with multiple cache modules, such as a CPU or an I/O device, typically use a cache coherency protocol to ensure that the cache memories remain consistent with each other and with main memory. Popular cache coherency protocols usually include an INVALIDATE transaction that signals cache memories to invalidate a cache line associated with the address contained in the transaction. A TLB in accordance with the present invention will observe the physical address contained in an INVALIDATE request and determine whether address lies within the page table. If it does, the physical address into the page table will be converted into a virtual page number. The TLB will then be accessed to see if the TLB contains an entry for the virtual page number.

Abstract: When memory size is increased by a factor of 2N (where N is an integer equal to or greater than unity) in a protocol-based memory system where a memory controller and multiple bus interfaces are interconnected via a bus, there exists a mismatch of N bits between the address format of each bus interface and that of the memory controller. In an initialization method for the memory system, one of the bus interfaces is enabled and request packets are transmitted successively from the memory controller to the enabled bus interface. Each packet contains a unique device identifier for identifying each bus interface. The packets of successive 2N arrivals are received at the enabled bus interface and an identifier for this bus interface is established using the device identifier contained in a predetermined one of the received packets by ignoring one or more device identifiers contained in other 2N−1 received packets.

Abstract: A memory control system employing at least one clock synchronous memory which is controlled by a memory control unit includes an interface circuit. The interface circuit functions as an output buffer synchronous with a clock. Thus, the interface circuit holds a memory control signal, which is output from the memory control unit for controlling the memory, and transmits the memory control signal to the memory in the predetermined time. In this configuration, access to the memory is made in consideration of the delay time required for a memory control signal to reach the memory via the interface circuit. Preferably, the presence or absence of the interface circuit for holding a memory control signal is determined based on an operation mode in which the memory control unit is established. Further proposed is a memory control method for controlling at least one clock synchronous memory which is implemented in the memory control system.