Patents Examined by Vu A Vu
  • Patent number: 11973320
    Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) includes a VCSEL array, a multitude of detectors, a first electrical laser contact, and at least one second electrical laser contact. The VCSEL array comprises a multitude of laser diodes, each laser diode including an optical resonator having a first distributed Bragg reflector, a second distributed Bragg reflector and an active layer for light emission, the active layer being arranged between the first distributed Bragg reflector and the second distributed Bragg reflector. The first electrical laser contact and the at least one second electrical laser contact are arranged to provide an electrical drive current to electrically pump the optical resonators of the laser diodes. Each detector is arranged to generate an electrical self-mixing interference measurement signal associated to at least one laser diode upon reception of the laser light.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 30, 2024
    Inventor: Philipp Henning Gerlach
  • Patent number: 11973041
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Patent number: 11967801
    Abstract: A structure having first and second layers is disposed on a substrate. The second layer is disposed on the first layer, is compressively strained, and comprises the alloy including germanium and tin. The structure comprises first and second members spaced a distance from each other along a direction, a strip located between the first and second members and extending along an axis intersecting the direction, and arms connecting the first and second members to a first end of the strip. The first and second members, the strip and the arms comprise respective portions of the first and second layers. A portion of the first layer at the strip and arms is removed such that the strip and arms become suspended and the arms remain anchored to the first layer via the first and second members. Tensile strain is induced in the alloy via the arms. The alloy may perform lasing.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 23, 2024
    Assignee: NanoPro AB
    Inventors: Ahmad Abedin, Mikael Östling
  • Patent number: 11955463
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 9, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11955767
    Abstract: In an embodiment a radiation-emitting component includes a first semiconductor chip configured to generate first primary electromagnetic radiation, a second semiconductor chip configured to generate second primary electromagnetic radiation, a first conversion element configured to partially convert the first and/or the second primary electromagnetic radiation into a first secondary radiation, wherein the first semiconductor chip is a first semiconductor laser diode, wherein the first primary electromagnetic radiation is blue primary radiation and wherein the first secondary radiation is green secondary radiation and a first optical element arranged between radiation emitting surfaces of the first semiconductor chip and the second semiconductor chip, wherein the first optical element is reflective for the first primary radiation and the second primary radiation.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 9, 2024
    Assignee: OSRAM OLED GmbH
    Inventors: Jörg Erich Sorg, David Racz
  • Patent number: 11948928
    Abstract: A display apparatus, including a circuit substrate, a driving unit and a light-emitting unit is provided. The driving unit is disposed on the circuit substrate. The light-emitting unit is disposed on the circuit substrate. A thickness of the driving unit is substantially the same as a thickness of the light-emitting unit.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Au Optronics Corporation
    Inventors: Yang-En Wu, Shih-Hsiung Lin
  • Patent number: 11948876
    Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Patent number: 11948911
    Abstract: The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 2, 2024
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Guoqing Yu
  • Patent number: 11942352
    Abstract: A manufacturing method of an LED display is disclosed. The method includes picking up a plurality of LED chips spaced apart at a first interval with a stretchable stamp, spacing apart the plurality of LED chips at a second interval by stretching the stretchable stamp, and transferring the plurality of LED chips to a target substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 26, 2024
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Dahl Young Khang, Byong Joo Lee
  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Patent number: 11942754
    Abstract: The present invention discloses a driving current correction method and apparatus for multiple laser devices, and a laser projector.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 26, 2024
    Assignee: GOER OPTICAL TECHNOLOGY CO., LTD.
    Inventors: Lebao Yang, Xianbin Wang
  • Patent number: 11942762
    Abstract: A surface-emitting laser device according to an embodiment comprises: a first electrode; a substrate arranged on the first electrode; a first reflection layer arranged on the substrate; an active region arranged on the first reflection layer and including a cavity; an opening region arranged on the active region and including an aperture and an insulation region; a second reflection layer arranged on the opening region; a second electrode arranged on the second reflection layer; and a delta doping layer arranged in the opening region. The thickness of the insulation region becomes thinner in the direction of the aperture, and the delta doping layer can be arranged at the aperture.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 26, 2024
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Jeong Sik Lee, Sang Heon Han, Keun Uk Park, Yeo Jae Yoon
  • Patent number: 11935777
    Abstract: A semiconductor device is manufactured using a support base and a filling material formed on the support base. The filling material can be a plurality of protrusions or penetrable film. The protrusions are attached to the support base with an adhesive. The protrusions have a variety of shapes such as square frustum, conical frustum, three-sided pyramid with a flat top, four-sided rectangular body, and elongated square frustum. A semiconductor wafer is disposed over the support base with the filling material extending into openings in the semiconductor wafer. The openings in the semiconductor wafer can have slanted sidewalls, or a more complex shape such as ledges and vertical projections. The filling material may substantially fill the openings in the semiconductor wafer. The protrusions may partially fill the openings in the semiconductor wafer. The protrusions occupy at least a center of the openings in the semiconductor wafer.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte Ltd.
    Inventors: HyeonChul Lee, HunTeak Lee, HyunSu Tak, Wanil Lee, InHo Seo
  • Patent number: 11935865
    Abstract: A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 19, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Tetsuro Sato
  • Patent number: 11929591
    Abstract: A semiconductor light-emitting device includes a stacked body, a cutout section, and a high-resistance region. The stacked body includes a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer in this order and has paired side faces opposed to each other. The cutout section is provided on at least one of the paired side faces of the stacked body and has a bottom face where the first conductive-type semiconductor layer is exposed. The high-resistance region is provided from the vicinity of the bottom face of the cutout section to the side face of the stacked body and has electric resistance higher than the electric resistance of the stacked body in a periphery of the high-resistance region.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 12, 2024
    Assignee: SONY CORPORATION
    Inventors: Masahiro Murayama, Takashi Sugiyama
  • Patent number: 11923214
    Abstract: A semiconductor packaging apparatus and methods of manufacturing semiconductor devices using the same. The semiconductor packaging apparatus includes a process unit, and a controller associated with the process unit. The process unit includes a bonding part that bonds a semiconductor substrate and a carrier substrate to each other to form a bonded substrate, a cooling part that cools the bonded substrate, and a detection part in the cooling part and configured to detect a defect of the bonded substrate. The controller is configured to control the process unit using data obtained from the detection part.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, Sang-Geun Park, Dongseok Baek, Jaehyuk Choi
  • Patent number: 11923659
    Abstract: A method for controlling a wavelength of an optical module, includes: a laser light source unit emitting a laser beam; a wavelength filter having a periodical transmission characteristic with respect to a wavelength of light; a temperature controller on which the wavelength filter is placed and that adjusting a temperature of the wavelength filter; a heat generating body placed on the temperature controller; and a control device controlling the wavelength of the laser beam emitted from the laser light source unit and control the transmission characteristic of the wavelength filter based on an intensity of the laser beam transmitted through the wavelength filter, the method including changing at least one of a target value of the wavelength control of the laser beam and a target value of the control of the wavelength filter based on a current value of the heat generating body.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: March 5, 2024
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayoshi Nishita, Atsushi Yamamoto
  • Patent number: 11916022
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
  • Patent number: 11915925
    Abstract: An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 ?m interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 27, 2024
    Assignee: DAICEL CORPORATION
    Inventor: Naoko Tsuji
  • Patent number: 11909174
    Abstract: A reflection filter device includes: a ring resonator filter including a ring-shaped waveguide and two arms, each of the two arms being optically coupled to the ring-shaped waveguide; and a dual-branch portion including a light input/output port and two branch ports, the light input/output port being configured to allow input and output of light, the two branch ports being configured to allow output of the light input from the light input/output port, the light being split into two, the two arms being connected to the two branch ports, respectively, at least one of the two arms being equipped with a phase adjuster.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 20, 2024
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yasumasa Kawakita, Yasutaka Higa