Abstract: Provided is a surface light emitting element having a high productivity, a high light emission output and good response characteristics, as well as capable of suppressing an increase of a forward voltage necessary for light emission. A surface light emitting element according to the present invention is a vertical cavity surface light emitting element including: an active layer 5 in which a quantum well layer 51 and a barrier layer 52 are alternately laminated; and reflective layers disposed both above and below the active layer 5, wherein assuming that a center-to-center distance of a plurality of the quantum well layers is L, a light emission wavelength of the surface light emitting element is ?, and an average refractive index of an optical length of a resonator, being a distance between the reflective layers is n, a condition of ?/(15×n)?L??/(10×n) is satisfied.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: A wafer assembly comprises a wafer having a MEMS layer formed on a frontside and a polymer coating covering the MEMS layer. A holding means is releasably attached to the polymer coating so that the wafer assembly facilitates performance of backside operations on a backside of the wafer. The polymer coating is comprised of a polymerized siloxane.

Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.

Abstract: A solution to failure mechanisms caused by mechanical sawing of a mechanical semiconductor workpiece entails use of a laser beam to cut and remove the electrically conductive and low-k dielectric material layers from a dicing street before saw dicing to separate semiconductor devices. A laser beam forms a laser scribe region such as a channel in the electrically conductive and low-k dielectric material layers, the bottom of the channel ending on a laser energy transparent stop layer of silicon oxide lying below all of the electrically conductive and low-k dielectric material layers. The disclosed process entails selection of laser parameters such as wavelength, pulse width, and fluence that cooperate to leave the silicon oxide layer stop layer completely or nearly undamaged. A mechanical saw cuts the silicon oxide layer and all other material layers below it, as well as the substrate, to separate the semiconductor devices.

Abstract: Process and system for processing wafer-shaped objects, such as semiconductor wafers is disclosed. In accordance with the present disclosure, a multiple of two wafers are processed in a thermal processing chamber. The thermal processing chamber is in communication with at least one heating device for heating the wafers. The wafers are placed in the thermal processing chamber in a face-to-face configuration or in a back-to-back configuration.

Abstract: Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.

Abstract: A method of forming a nitride semiconductor through ion implantation and an electronic device including the same are disclosed. In the method, an ion implantation region composed of a line/space pattern is formed on a substrate at an ion implantation dose of more than 1E17 ions/cm2 to 5E18 ions/cm2 or less and an ion implantation energy of 30˜50 keV, and a metal nitride thin film is grown on the substrate by epitaxial lateral overgrowth, thereby decreasing lattice defects in the metal nitride thin film. Thus, the electronic device has improved efficiency.

Abstract: A method for forming a thin-film transistor gate insulating layer over a substrate disposed in a processing chamber is provided. The method includes: introducing a processing gas for producing a plasma in the processing chamber; heating the substrate to a substrate processing temperature of between 50 and 350° C.; and depositing silicon oxide, silicon oxynitride, or silicon nitride over the heated substrate by sputtering a target assembly at a medium frequency.

Abstract: A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.

Abstract: A method of manufacturing a package including manufacturing a substrate to include at least one layer of LCP material, manufacturing a cover made of LCP material to include a lower lip, and sealing the cover to the substrate by heating the interface between the lower lip and the substrate.

Abstract: An electronic component or display device of the present invention can be provided by using a following pattern formation method. On a substrate treated with a first etching with a first resist pattern as a first mask, a second resist pattern is transfer-printed on the first resist patterns so as to partially overlap with the first resist pattern and partially extended from the first resist pattern. And then a second etching is performed by using the first resist pattern and the second resist pattern as a second mask. The first resist pattern and the second resist pattern are used for forming wirings and/or terminals, and the extended portion of the second resist pattern is used to make the wirings to have a cross section of a stair-like edge shape.

Abstract: Various embodiments of the present invention are related to microresonator systems and to methods for fabricating the microresonator systems. In one embodiment, a method of fabricating a microresonator system comprises: forming a multilayer system having a bottom layer, a top layer, and an intermediate layer having one or more quantum wells and sandwiched between the bottom layer and the top layer; embedding at least one waveguide in a substrate having a top surface, the at least one waveguide positioned adjacent to the top surface of the substrate; wafer bonding the top layer of the multilayer system to the top surface of the substrate; forming a microresonator in the multilayer system, wherein at least a portion of a peripheral annular region of the microresonator is portioned above the at least one waveguide; and forming a current isolation region in at least a portion of a central region of the microresonator.

Abstract: Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs).

Abstract: A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.

Abstract: The present invention relates to relates to a semiconductor package having a function of shielding electromagnetic interference (EMI), a manufacturing method thereof and a jig, and more particularly, to such a semiconductor package having an electromagnetic interference (EMI)-shielding function, a manufacturing method thereof and a jig for use in a plasma sputtering, in which a nickel alloy is coated on the surface of a semiconductor package by a sputtering method so as to shield electromagnetic interference (EMI) generated from the semiconductor package.

Abstract: The present invention provides a recovery processing method to restore the substrate processing apparatus to an operating state after correcting an abnormality having occurred in the substrate processing apparatus in operation and having resulted in a stop in the operation, comprising a substrate retrieval step in which substrate salvage processing is first executed for a wafer W left in a chamber in the substrate processing apparatus in correspondence to the extent to which the wafer has been processed at the time of the operation stop and the substrate having undergone the substrate salvage processing is then retrieved into the cassette storage container and an apparatus internal state restoration step in which the states inside the individual chambers of the substrate processing apparatus are restored.

Abstract: A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.