Abstract: Successive layers of a II-VI ternary buffer layer and a II-VI ternary nar-bandpass infrared-absorbing layer are grown by MBE on a III-V binary substrate with low surface defect density. The composition of the buffer layer is chosen to lattice match with the infrared-absorbing layer.

Abstract: An electron device resembling a MOS capacitor with two opposed terminals, except that the central dielectric substance includes a centralsemiconductor layer connected to a third terminal. An information carrying signal traveling depthwise through the layers is controlled by the variation of the depletion layers that are formed depthwise opposite each other by the action of the top and bottom electrodes. This control action takes the form of modulation of displacement current in the central dielectric substance. Pulse edge biasing of the device can cause two opposed depletion layers to approach each other in the central semiconductor layer achieving punch-through. An inverter circuit, formed by a pair of these devices forms the basis for a logic family. A transmission line, an EAROM, and a single-cell static random access memory are integrated circuit applications of the device.

Abstract: A low-loss P-i-n diode includes an i-type layer consisting of first and second i-type regions formed on the cathode layer of the diode and the i-type has a thickness W.sub.i of less than 25 .mu.m. The impurity concentration of the first i-type region is higher than that of the second i-type region. To obtain a good forward-voltage V.sub.f, W.sub.i.sup.2 /.tau. is selected to be in the range of 20-200cm.sup.cm.sup.2/sec and the carrier lifetime .tau. of the i-type layer is controlled by a carrier lifetime killer with a small resistivity compensation effect which is diffused into the i-type layer. The P-i-n diode has a high reverse breakdown voltage, small forward-voltage drop and a short recovery time.

Abstract: A thin film image pickup element which consists of a photoelectric converter including a transparent electrode, a semiconductor layer, an opaque electrode and first insulator layer, and a switching element including first and second upper electrodes, another semiconductor layer, a gate electrode and a passivation film covered on the gate electrode. A two-dimensional thin film image pickup device consists of a plurality of such thin film image pickup elements by stereoscopically laminating a plurality of photoelectric converters and switching elements with the back surface used as wiring region. The device can read two-dimensional original documents without using a reducing optical system.

Abstract: A semiconductor device (1) including a monocrystalline region of semiconductor grey tin material (5) in intimate contact with a monocrystalline substrate (3). The region of semiconductor tin (5) is stabilized by interaction with the monocrystalline substrate (3) which has a crystallographic structure isomorphous with the structure of grey tin and an interatomic spacing matched to the interatomic spacing of the semiconductor region (5). The semiconductor region (5) may be further stabilized by inclusion of germanium dopant. The matching substrate (3) may be of indium antimonide, cadmium telluride, germanium or silicon material. Ohmic contact between a region of semiconductor tin (5) and a region of metal white tin (15) may be formed. Details of infra-red photovoltaic and photoconductive devices are given.The semiconductor region of tin may be grown by molecular beam epitaxy.

Abstract: In a light-activated semiconductor device wherein a light-activated semiconductor element accommodated in a package is driven by a light signal fed from an external light source into the package through an optical guide, the optical guide comprises a first portion passing through the package and a second portion for optically coupling the first portion and the light-activated element.

Abstract: An n-p-.pi.-p.sup.+ Si avalanche photodiode wherein the number of acceptors introduced into a Si body to form the p-type conductivity region has been reduced and this region extends a distance greater than about 35 micrometers into the body from the surface and wherein the n-type conductivity region extends a distance into the body such that the p-n junction is less than about 10 micrometers from the surface of the body. The method of the invention comprises introducing a reduced number of acceptors into the surface of the body, diffusing the acceptors into the body a distance greater than about 35 micrometers and forming an n-type conductivity region such that the p-n junction is less than 10 micrometers from the surface of the device. APDs of the invention exhibit a k.sub.eff of about 0.006 which is a factor of greater than 2.5 less than that of typical prior art devices.

Abstract: An integrated circuit element which is laterally insulated by oxide includes a transistor and a resistor. The resistor is formed by an elongation of the base and includes an emitter of the transistor. A pinching zone is present beneath the emitter and is selectively doped with respect to a pinching zone located beneath a further emitter of the transistor. The integrated circuit element may be combined with another substantially identical element to form a compact memory cell.

Abstract: The invention is an APD array having a plurality of p-n junctions. The p-n junctions comprise a plurality of separate regions which extend a distance into a semiconductor body from a surface thereof and have a conductivity type opposed to that of the body. A region of the same conductivity type as that of the body extends a further distance into the body and is composed of sub-regions which overlap one another in the direction parallel to the surface of the body. The elements so formed have a more uniform avalanche gain and, because of the overlap of the sub-regions of first conductivity type, the likelihood of electric breakdown at the surface is reduced and the electrical isolation between the elements is increased. Moreover, because of the proximity of the adjacent elements the likelihood of breakdown at the junction edges is reduced.

Abstract: A carrier for LSI chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip with the plates of the capacitor parallel to the chip mounting surface or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments together to form the first one of the plates of a capacitor with the other plate spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines which extend up to a severable link on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of the capacitor.

Abstract: A variable capacitor comprises a plurality of variable capacity elements each having depletion layer control section and a capacity reading section both formed on a semiconductor substrate so that the capacity appearing at each capacity reading section varies in accordance with the bias voltage applied to the depletion layer control sections. Portions of the semiconductor substrate where the capacity reading sections are formed have different carrier concentrations, respectively, so that the capacity read out at the capacity reading section also varies in accordance with the carrier concentration.

Abstract: A photoconductive image pick-up tube target comprising an N-type semiconductor film formed on a transparent substrate, and a P-type photoconductive film in rectifying contact with the N-type semiconductor film and containing Se and As and also Te as sensitizers. A layer of said P-type photoconductive film between the N-type semiconductor film and a Te-containing layer of the P-type photoconductive film has an As concentration distribution which is lower on the side of the N-type conductive film and higher on the side of the Te-containing layer.

Abstract: An electro-optic integrated circuit is disclosed wherein the long electrical connections normally present on a large scale integrated circuit are replaced by an optical waveguide layer. A plurality of epitaxial layers are grown on a single substrate and at least three of the plurality of epitaxial layers are grown with bandgaps that are suitable for optical sources, detectors and waveguiding. These primary layers are separated from each other by a barrier layer having a bandgap greater than either of the adjacent primary layers. Two of the layers adjacent to the substrate are grown to accommodate electrical devices that can be used to couple electrical signals to the optical source layers and to amplify electrical signals provided by the optical detection layer.

Abstract: There is disclosed a semiconductor device having a PN junction terminating at a surface and passivated by a multi-layer passivant system comprising a first layer of semi-insulating material over the surface, a layer of dielectric material over the first layer and a second layer of semi-insulating material over the dielectric layer. Preferably, the first and second layers are oxygen doped polycrystalline silicon and the dielectric layer is either silicon dioxide of frit glass fused to the first layer.