Patents Examined by Wael Faburry
  • Patent number: 6551882
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: April 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa