Abstract: Within a method for fabricating a semiconductor substrate while employing formed thereover a mask layer there is first employed the mask layer as an etch mask layer for forming a pair of isolation trenches within the semiconductor substrate and then laterally etched the mask layer prior to employing the laterally etched mask layer as an oxidation mask layer. By laterally etching the mask layer, there is formed within the semiconductor substrate a continuously curved convex elevated region as an active region of the semiconductor substrate.

Abstract: A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the presence of an amount of passivating agent that is sufficient to impede subsequent reaction of at least a top half of the layer of refractory metal with the first conductive layer and is less than an amount of passivating agent necessary to form a stoichiometric refractory metal with the passivating agent, and annealing the refractory metal and the first conductive layer in a first element ambient, thereby forming a stoichiometric refractory metal with the first element in at least a portion of the top half of the layer of refractory metal.

Abstract: A single circuit element, referred to as a solid state rectifying fuse (SSRF), rectifies an incoming AC signal and opens the circuit if a programmed maximum current level is reached. The anode or cathode depending upon the particular application is designed with a plurality of conductors strips in electrical contact with the P or N region, respectively. Conductor strips are composed of a material that melts open if the current limit is exceeded. Conductor strips are designed to have a lower total current handling capacity than that of the PN junction so that the current is reduced or terminated before the PN junction can “short.” Depending on the desired maximum current of the SSRF, the current limit can be adjusted downward by burning out or severing some of the conductors. In this sense, it is a programmable diode.

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches.

Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane.

Abstract: A semiconductor device (A) includes a first lead (4) to which a semiconductor chip (1) is bonded, a second lead (5) connected to the semiconductor chip (1) via a wire (W), and a resin package (2) sealing the semiconductor chip (1) and the wire (W). Of the first and the second leads (4, 5), at least one of inner terminals (4a, 5b) enclosed in the resin package (2) is bent in a direction of a thickness of the resin package (2).

Abstract: A contact opening (940) is provided in a dielectric layer (720) overlaying a gate electrode (840). The contact opening and gate electrode are of substantially the same width, thus allowing for minimized area contact. A pair of process buffering regions (810) situated along the sidewalls of the gate electrode furnish additional landing area for the contact opening without exposing the sidewalls of the gate electrode.

Abstract: In the ESD protection configuration, in addition to the existing protection configurations, at each supply pad of the supply bus, an ESD diode is also inserted between the power bus with the potential VSSP and the supply bus with the supply potential VDDP. This ESD diode closes the protection path for negative loads between the substrate potential VSSB and the potential VSSP during an ESD stress and limits the voltage difference occurring between the two corresponding buses (the substrate bus and the power bus) to the terminal voltage of the breakdown diode plus the forward voltage of the ESD diode. The ESD diode between the power bus and the supply bus is intended to be operated only in the forward direction. This requires the breakdown voltage of the ESD diode to be significantly above the breakdown voltage of the breakdown diode of the supply bus.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: Two conductors of the same layer are separated by a low-K dielectric to minimize capacitance between them. The first and second conductors may have sidewalls with conductive barriers. The conductive barriers are separated from the low-K dielectric by spacers. The dielectric spacers have a top portion and a lower portion in which the top portion may have a higher dielectric constant than the lower portion or may be the same material. The two conductors are formed in trenches in a convenient dielectric. Prior to forming the conductors, the conductive barriers are deposited in the trench. After the conductors are formed, the convenient dielectric is removed. The dielectric spacers are formed adjacent to the conductive barriers. The low-K dielectric is then deposited adjacent to the dielectric spacers and not in contact with the conductive barriers.

Abstract: An integrated circuit package comprising a substrate, and a chip die mounted on the substrate. The substrate includes electrically conductive traces, a set of primary interconnects arranged to couple to output pads of the chip die, and a set of secondary interconnects for coupling the package to external circuitry. A first subset of the primary interconnects are electrically coupled to the secondary interconnects and a second subset of the primary interconnects are thermally coupled using thermal vias to the opposite surface of the substrate. The output pads associated with the first subset of the primary interconnects therefore function as electrically interconnecting pads whereas the output pads associated with the second subset of the primary interconnects function as non-electrically interconnecting thermal-dissipation pads.

Abstract: Shallow trench isolation techniques are disclosed in which a nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate. The nitride layer is removed prior to filling the isolation trench, and the fill material is planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process.

Abstract: A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

Abstract: A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.

Abstract: A compound semiconductor device is provided that includes a substrate and an active region disposed above the substrate. The active region includes at least two different pseudomorphic layers, the first layer having the form InxGa1−xPyAszSb1−y−z, and the second layer having the form InqGa1−qPrAssSb1−r−s. The first layer includes at least In, Ga, and As, and the second layer includes at least Ga, As, and Sb. It is preferable for the substrate to be GaAs or AlpGa1−pAs (0<p<1), or to have a lattice constant close to or equal to that of GaA For the first layer, it is preferable if x is between 0.05 and 0.7, y is between 0 and 0,35, z is between 0.45 and 1, and 1−y−z is between 0 and 0.25. For the second layer, it is preferable if q is between 0 and 0.25 and 1−r−s is between 0.25 and 1.

Abstract: An electronic package comprising a semiconductor chip mounted on a substrate is formed by bonding a structure which covers at least an outer surface of the semiconductor chip and has the same or about the same thermal expansion coefficient as the substrate to the semiconductor chip's side surface of the substrate. This reduces warp and deformation caused by temperature changes during package operation.

Abstract: A first guard ring formed by high concentration ion diffusion is established around the transistor formation region of the semiconductor substrate. A second guard ring is established around the first guard ring with a prescribed gap therebetween. A metal film is formed opposing to each guard ring with an insulating film interposed therebetween; these metal films are connected to the opposing guard rings by interlayer wires. The metal films are each connected to external terminals providing a standard potential by individual metal wires from their respective electrodes.

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.