Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

Abstract: There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible.

Abstract: Systems and methods are provided that provide a getter in a micromechanical system. In some embodiments, a microelectromechanical system (MEMS) is bonded to a substrate. The MEMS and the substrate have a first cavity and a second cavity therebetween. A first getter is provided on the substrate in the first cavity and integrated with an electrode. A second getter is provided in the first cavity over a passivation layer on the substrate. In some embodiments, the first cavity is a gyroscope cavity, and the second cavity is an accelerometer cavity.

Abstract: A sensor is disclosed. The sensor comprises a first substrate; a second substrate positioned relative to the first substrate; a first electrode located between the first substrate and the second substrate, the first electrode formed on the second substrate; a sensing portion covering at least a part of the first electrode and further covering at least a portion of the second substrate; a pad electrode located between the first substrate and the second substrate, wherein the pad electrode is formed on the second substrate and is electrically coupled to the first electrode; and a bonding pad located between the first substrate and the second substrate, wherein the bonding pad is formed on the first substrate and is electrically coupled to the pad electrode.

Abstract: An organic light emitting display device includes a display panel including a display region where a plurality of pixels are disposed, a pad region including a bending region and a pad electrode region where pad electrodes are disposed, a polarizing layer disposed in the display region, and a lower protection film disposed on a lower surface of the display panel. The lower protection film includes a first and a second lower protection film pattern. The first lower protection film pattern is disposed in the display region, and the second lower protection film pattern in the pad electrode region such that a lower surface of the display panel in the bending region is exposed. The bending protection layer has an upper surface with a height that is less than a height of the polarizing layer, and is disposed in the bending region on the display panel.

Abstract: An image sensor is disclosed. The image sensor includes: a common node heavily doped with dopants of a first conductivity type, the common node being within the substrate and abutting the front surface of the substrate; and a sensing node heavily doped with dopants of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and abutting the front surface of the substrate; an interconnect structure, wherein the front surface of the substrate faces the interconnect structure; a distributed Bragg reflector (DBR) between the front surface of the substrate and the interconnect structure; a first contact plug passing through the DBR and coupling the common node to the interconnect structure; and a second contact plug passing through the DBR and coupling the sensing node to the interconnect structure.

Abstract: An ion-sensitive structure includes a semiconductor structure and a layer stack disposed on the semiconductor structure having a doped intermediate layer including a doping material and a first metal oxide material. The semiconductor structure is configured to change an electric characteristic based on a contact of the ion-sensitive structure with an electrolyte including ions.

Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A light emitting device can include a light emitting structure including a p-GaN based layer, an active layer having multiple quantum wells, and an n-GaN based layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, in which the n-electrode has a plurality of layers; a phosphor layer disposed on a top surface of the light emitting structure; and a passivation layer disposed between the phosphor layer and the top surface of the light emitting structure, and disposed on outermost side surfaces of the light emitting structure, in which the p-electrode and the n-electrode are disposed on opposite sides of the light emitting structure. Also, the phosphor layer has a two-digit micrometer thickness, and includes a pattern to bond an n-electrode pad on a portion of the n-electrode by a wire, and comprises different phosphor materials configured to emit light of different colors.

Abstract: Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.

Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.

Abstract: This method for controlling an IGBT-type transistor includes a phase for switching the transistor between an on state and an off state. Said phase comprises generating a setpoint current whereof the intensity on the gate of the transistor assumes different setpoint values. At least some of the setpoint values are chosen as a function of the sign of the temporal derivative of the main current. Each setpoint value is chosen from a set of predetermined setpoint values.

Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.

Abstract: An organic light emitting device is disclosed whose emissive layer has a host material, a first emissive dopant, and a second dopant. The second dopant is an excited energy state managing dopant provided in an amount between 2-10 vol. % of the emissive layer and has a lowest triplet state energy level, TM, that is higher than a lowest triplet state energy levels, T1, of both the host and the first dopant and lower than the multiply-excited energy level, T*, of the first dopant.