Abstract: A method of fabricating an STI structure comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. A hard mask layer is formed over the pad oxide layer. The hard mask layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure. The opening having exposed side walls. A spacer layer is formed over the patterned hard mask layer, the exposed side walls of the opening and lining the opening. The structure is subjected to an STI trench etching process to: (1) remove the spacer layer from over the patterned hard mask layer; form spacers over the side walls; (2) the spacers being formed in-situ from the spacer layer; and (3) etch an STI trench within the silicon structure wherein the spacers serve as masks during at least a portion of time in which the STI trench is formed. The STI trench having corners. Any remaining portion of the spacers are removed.

Abstract: A supercritical etching composition and method for etching an inorganic material of a semiconductor-based substrate are provided. The method includes providing a semiconductor-based substrate having an exposed inorganic material and exposing the substrate to the supercritical etching composition, whereby exposed inorganic material is removed from the substrate. In one embodiment, the supercritical etching composition includes a supercritical component, which is not capable of etching a particular exposed inorganic material, and a nonsupercritical etching component, which is capable of etching the particular exposed inorganic material. In another embodiment, the supercritical etching composition includes a supercritical component, which is capable of etching the particular exposed inorganic material.

Abstract: A polishing apparatus is used for chemical mechanical polishing a copper (Cu) layer formed on a substrate such as a semiconductor wafer and then cleaning the polished substrate. The polishing apparatus has a polishing section having a turntable with a polishing surface and a top ring for holding a substrate and pressing the substrate against the polishing surface to polish a surface having a semiconductor device thereon, and a cleaning section for cleaning the substrate which has been polished. The cleaning section has an electrolyzed water supply device for supplying electrolyzed water to the substrate to clean the polished surface of the substrate while supplying electrolyzed water to the substrate.

Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction.

Abstract: This invention is directed to a novel process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon. In one embodiment, an epitaxial layer is deposited onto a surface of a silicon wafer. The wafer is also heated to a temperature of at least about 1175° C. This heat treatment begins either during or after the epitaxial deposition. Following the heat treatment, the heated wafer is cooled for a period of time at a rate of at least about 10° C./sec while (a) the temperature of the wafer is greater than about 1000° C., and (b) the wafer is not in contact with a susceptor. In this process, the epitaxial deposition, heating, and cooling are conducted in the same reactor chamber.

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

Abstract: An antistatic polymer film having a coated surface that resists the formation of static. The antistatic coating on the film layer includes a polythiophene, a surfactant and water. The ratio of the surfactant to the polythiophene can be at least about 1:1 by weight of said coating. In addition, the coating can contain less than about 1 percent by weight of polymeric binder and can also contain less than about 1 percent by weight of organic solvent.

Abstract: A method is proposed for producing three-dimensional structures, especially microlenses, in a substrate using an etching process, at least one original shape having a known original surface shape being present initially on the substrate in a plurality of places. The etching process has at least one first etching removal rate a1 and a second etching removal rate a2 which are material-dependent, and of which at least one is changeable as a function of time. The original shape is converted to a target shape by the etching process, the original surface shape of the original shape and the target surface shape of the target shape to be reached being known before the beginning of the etching process. In order to achieve the target surface shape, at least one of the etching rates a2 or a1 is set by a change of at least one etching parameter calculated before the beginning of the etching process as a function of the etching time.

Abstract: Embodiments of the present invention are directed to method of fabrication of a broadband emitter array. Embodiments of the present invention may grown a first set of emitters possessing a first quantum well characteristic (e.g., quantum well thickness or composition). A portion of the first set of emitters is removed by etching. In place of the removed emitters, a second set of emitters is regrown with said second set of emitters possessing a different quantum well characteristic. By fabricating the emitters sets in this manner, a unitary emitter array may be fabricated that possesses an increased bandwidth, e.g., the first and second sets of emitters may be associated with different center wavelengths. Embodiments of the present invention may utilize emitter arrays fabricated in this manner in, for example, incoherently beam combined (IBC) lasers and in Raman amplifier systems.

Abstract: Reactive atom plasma processing can be used to shape, polish, planarize, and clean surfaces of difficult materials with minimal subsurface damage. The apparatus and methods use a plasma torch, such as a conventional ICP torch. The workpiece and plasma torch are moved with respect to each other, whether by translating and/or rotating the workpiece, the plasma, or both. The plasma discharge from the torch can be used to shape, planarize, polish, clean and/or deposit material on the surface of the workpiece, as well as to thin the workpiece. The processing may cause minimal or no damage to the workpiece underneath the surface, and may involve removing material from, and/or redistributing material on, the surface of the workpiece.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120, 122 and 128 of FIGS. 1a-1d) comprised of a metal; forming a dielectric layer (layer 130 of FIGS. 1a-1d) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material 136 and 137 of FIG. 1c) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer.

Abstract: A process tool comprised of an adjustable wafer stage and various methods and systems for performing process operations using same is disclosed herein. In one illustrative embodiment, the process tool is comprised of a process chamber, and an adjustable wafer stage in the process chamber to receive a wafer positioned thereabove, the wafer stage having a surface that is adapted to be raised, lowered or tilted. In further embodiments, the process tool further comprises at least three pneumatic cylinders or at least three rack and pinion combinations, each of which are operatively coupled to the wafer stage by a ball and socket connection.

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.

Abstract: Methods and apparatus for controlling the temperature of a process surface and for conditioning of a process surface are provided. In one example, a temperature controller is described within a CMP system. The CMP system has a first roller and a second roller and a linear belt circulating around the first and second rollers. The linear belt has a width that spans between a first edge and a second edge. The temperature controller includes an array of thermal elements. Each of the thermal elements of the array is independently controlled. The array of thermal elements is positioned between the first roller and the second roller and configured to contact a back surface of the linear belt. The array of thermal elements extends between the first edge and the second edge of the linear belt width.

Abstract: Problems caused by a nonuniform processing profile are avoided by altering the area to be processed so as to compensate for the processing profile. More specifically, with regard to etching, problems caused by a nonuniform etch profile can be avoided by altering the mask employed in specifying the etch area so as to compensate for the etch profile. Nonuniform parameters of interest of structures which result from a nonuniform etch profile during the etching of a mask in which all the structures were identical can be avoided for by altering the mask employed in specifying the etch area so as to compensate for the etch profile. The mask is changed in a manner that is inversely proportional to the etch profile for each particular structure characteristic that determines the parameter of interest for which uniformity is desired.

Abstract: The present invention intends to provide an agent and a method for removing harmful gas, which exhibits high harm-removing ability per unit volume for harmful halogen-containing gas contained in the exhaust gas from the etching or cleaning step in the manufacturing process of a semiconductor device, and which is inexpensive. The invention is characterized by that halogen-containing gas is removed using a harm-removing agent comprising a specific iron oxide, an alkaline earth metal compound and activated carbon in the specific amount. In the case where the exhaust gas contains halogen gas such as chlorine or a gas such as sulfur dioxide, the gas is rendered harmless by using in combination a harm-removing agent comprising activated carbon or zeolite.

Abstract: A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.

Abstract: A variety of etching bath-based demetallizing processes for making various products involve immersing a web of metal-containing material in a bath of aqueous etchant. The metal-containing material is protected by a pattern of etch-resistant material during the demetallizating process to form functional features having a function in the product in the metal-containing material when the web has been demetallized. The metal-containing material is also protected by a pattern of etch-resistant material over areas of the metal-containing material that serve no function in the product, but rather function in one or more ways to improve the chemical milling process, such as, for example, by extending the etchant bath life, preventing excessive heat generation in the etchant bath, maintaining the etchant bath stable and controllable, increasing web rigidity, and imparting predetermined flex characteristics to the web.