Abstract: A phase-change random access memory (PRAM) device and a method of manufacturing the same are provided. The PRAM device includes a semiconductor substrate in which a switching device is formed, a lower electrode configured to be formed on the switching device and having a void formed in a portion of an upper surface thereof, and a phase-change layer configured to be formed on the lower electrode having the void.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.

Abstract: Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.

Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle ? other than 90° with respect to the gate direction.

Abstract: A method for manufacturing a transparent electrode using a print-based metal wire is provided, which enables the mass production of the transparent electrode as a substitute for ITO at low cost. The manufacturing method includes: the first step of forming a metal wire in a pattern set for a transparent substrate; and the second step of coating a solution type transparent electrode on the transparent substrate.

Abstract: A new, more economical method for preparing titania pastes for use in more efficient dye-sensitized solar cells is disclosed. The titania pastes are prepared by mixing titania nanoparticles with a titania sol including a titanium precursor. The disclosed method enables the control of titania nanoparticle concentration and morphology in the titania paste and is economical due to the relatively low reaction temperatures. The performances of dye-sensitized solar cells prepared using the disclosed titania pastes are also disclosed.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: A method for etching with a laser beam having a predetermined wavelength an area of a layer of a first material, said area being deposited at the surface of at least two second materials, includes: depositing a layer of a third material on the layer of the first material, the first and the third materials having a chemical affinity on application of the laser beam greater than the chemical affinity during said application between the first material and each of said at least two second materials; and applying the laser beam to an area of a free surface of the layer of third material vertically above the area of the layer of first material with a fluence of said laser beam causing the separation of said area.

Abstract: A backside illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a front surface of a semiconductor substrate. Silicon inner microlenses may be formed on a back surface of the semiconductor substrate. In particular, positive inner microlenses may be formed over the photodiodes, whereas negative inner microlenses may be formed over the associated pixel circuits. Buried light shielding structures may be formed over the negative inner microlenses to prevent pixel circuitry that is formed in the substrate between two neighboring photodiodes from being exposed to incoming light. The buried light shielding structures may be lined with absorptive antireflective coating material to prevent light from being reflected off the surface of the buried light shielding structures.

Abstract: A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions.

Abstract: A method for making a semiconductor device may include forming a plurality of semiconductor fins on a substrate, forming a gate overlying the plurality of semiconductor fins, forming respective unmerged semiconductor regions on the semiconductor fins on opposing sides of the gate, and forming a dielectric layer overlying the unmerged semiconductor regions. The method may further include etching the dielectric layer to define contact recesses having recess bottoms exposing the unmerged semiconductor regions, forming a respective semiconductor layer on each of the exposed unmerged semiconductor regions to extend outwardly from adjacent portions of the recess bottom, and siliciding each of the semiconductor layers to define respective source and drain contacts extending outwardly from adjacent portions of the recess bottom.

Abstract: A semiconductor light emitting device includes: a package which is made of a resin and includes a recess; a lead frame exposed to a bottom of the recess; a semiconductor light emitting element connected to the lead frame in the recess; a phosphor layer over the bottom of the recess; and a second resin layer above the phosphor layer and the semiconductor light emitting element, in which the phosphor layer contains a semiconductor fine particle having an excitation fluorescence spectrum which changes according to a particle size, and the phosphor layer includes a water-soluble or water-dispersible material.

Abstract: A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes.

Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.

Abstract: A nitride semiconductor light-emitting element uses a non-polar plane as its growing plane. A GaN/InGaN multi-quantum well active layer includes an Si-doped layer which is arranged in an InyGa1-yN (where 0<y<1) well layer, between the InyGa1-yN (where 0<y<1) well layer and a GaN barrier layer, or in a region of the GaN barrier layer that is located closer to the InyGa1-yN (where 0<y<1) well layer. A concentration of Si at one interface of the GaN barrier layer on a growing direction side is either zero or lower than a concentration of Si in the Si-doped layer.

Abstract: A device includes a semiconductor substrate, a black reference circuit in the semiconductor substrate, a metal pad on a front side of, and underlying, the semiconductor substrate, and a first and a second conductive layer. The first conductive layer includes a first portion penetrating through the semiconductor substrate to connect to the metal pad, and a second portion forming a metal shield on a backside of the semiconductor substrate. The metal shield is aligned to the black reference circuit, and the first portion and the second portion are interconnected to form a continuous region. The second conductive layer includes a portion over and contacting the first portion of the first conductive layer, wherein the first portion of the first conductive layer and the portion of the second conductive layer form a first metal pad. A dielectric layer is overlying and contacting the second portion of the first conductive layer.

Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.